Half-Bridge Level Shift Circuit for dv/dt Noise-Resistant Switching
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Solution Overview
Problem
The level shift circuit in half-bridge drive circuits experiences delays in turning on the high side switching element due to dv/dt noise, leading to power loss in the diode connected in parallel, as the latch malfunction protection circuit blocks the set signal until the dv/dt noise period is finished, causing a significant delay in switching operations.
Innovation Solution
A level shift circuit configuration that includes a series circuit of resistors and switching elements, a latch malfunction protection circuit, and a logic gate circuit, which allows signal transmission to the latch circuit only when either switching element is turned on and not both, and uses feedback circuits to manage voltage levels, thereby reducing the impact of dv/dt noise and accelerating the switching operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the latch malfunction protection circuit blocks the set signal during dv/dt noise period, then the reliability of the latch circuit is improved, but the switching speed of the high side switching element deteriorates
Solution Approach 1:
The patent segments the protection mechanism by introducing a dedicated detection circuit that monitors dv/dt noise separately from the main signal path. This allows the set signal to be transmitted through the latch circuit while the detection circuit independently identifies and responds to noise conditions, preventing false blocking of valid signals while maintaining protection functionality.
Solution Approach 2:
The patent introduces an intermediary detection circuit between the set signal source and the latch circuit. This intermediary component detects dv/dt noise conditions and controls the timing of signal transmission, allowing the system to distinguish between noise-induced voltage changes and legitimate set signals, thereby enabling timely switching without compromising reliability.
2Speed
If the level shift circuit transmits the set signal immediately, then the switching speed is improved, but the latch circuit may malfunction due to dv/dt noise
Solution Approach 1:
The patent implements preliminary action by having the detection circuit continuously monitor for dv/dt noise conditions before the set signal is transmitted. The system prepares in advance by detecting noise patterns and timing the signal transmission to occur during safe windows when noise interference is minimal, thus enabling fast response while preventing latch malfunction.
Solution Approach 2:
The patent employs feedback mechanisms where the detection circuit continuously monitors the voltage conditions and dv/dt noise levels, and this information feeds back to control the timing of set signal transmission. The system adjusts signal transmission timing based on real-time noise detection, creating a closed-loop control that optimizes both speed and reliability.
3Reliability
If the high side switching element is delayed in turning on, then the latch circuit reliability is improved, but the power loss in the diode increases
Solution Approach 1:
The patent introduces dynamic timing control where the set signal transmission timing is adjusted in real-time based on detected dv/dt noise conditions. Rather than using a fixed delay, the system dynamically determines the optimal transmission moment, enabling the high side switching element to turn on as early as possible when safe, thereby minimizing diode conduction time and power loss while maintaining reliability.
Solution Approach 2:
The patent changes the timing parameter of set signal transmission based on detected noise conditions. By monitoring dv/dt levels and adjusting the transmission timing parameter dynamically, the system optimizes the balance between reliability and energy efficiency, allowing earlier switching when noise is low and preventing malfunction when noise is high, thus minimizing overall power loss.
Data Source
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AI summary
There is provided a level shift circuit that suppresses a delay caused by a circuit counteracting dv/dt noise in an operation of turning on a high side switching element configuring a half-bridge. The circuit includes a series circuit of a resistor LSR1 and a switching element HVN1 connected between a high voltage side power source voltage of a secondary side voltage system and a low voltage side power source voltage of a primary side voltage system, a series circuit of a resistor LSR2 and a switching element HVN2 connected between the high voltage side power source voltage of the secondary side voltage system and the low voltage side power source voltage of the primary side voltage system, a latch malfunction protection circuit 22, operating on the secondary side voltage system, into which is input the voltage of a connection point P1 of the resistor LSR1 and switching element HVN1 and the voltage of a connection point P2 of the resistor LSR2 and switching element HVN2, a latch circuit 23, operating on the secondary side voltage system, into which is input the output of the latch malfunction protection circuit 22, a switching element PM1a connected in parallel to the resistor LSR1, a switching element PM2a connected in parallel to the resistor LSR2, and a logical sum circuit OR1, operating on the secondary side voltage system, into which are input the voltages of the connection points P1 and P2, and which controls the turning on and off of the switching elements PM1a and PM2a.