Level Shift Circuit With Edge Delay Compensation for Duty Ratio
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Solution Overview
Problem
In semiconductor devices, a large difference between the delay times of the rising and falling edges of the output voltage leads to increased deviation in the duty ratio, reducing the operation margin due to the mismatch in delay times across level shift units.
Innovation Solution
A level shift circuit design where the delay time of the rising edge from one unit is compensated by the falling edge of the next unit, and vice versa, using multiple level shift units connected in series with inverters to adjust and synchronize the output voltage levels across different power supply potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple level shift units are connected in series to shift voltage levels, then the voltage level transformation is achieved, but the delay time difference between rising and falling edges increases
Solution Approach 1:
The patent introduces asymmetric delay compensation by connecting inverters with different numbers of series switches to adjacent level shift units. Specifically, when a rising edge passes through a level shift unit, the adjacent inverter compensates with a delay corresponding to one series switch; when a falling edge passes through, the compensation delay corresponds to two series switches. This asymmetric compensation approach balances the overall delay times for rising and falling edges, resolving the delay time mismatch problem while maintaining voltage level transformation capability.
2Adaptability or versatility
If the delay time difference between rising and falling edges is large, then the level shifting function is achieved, but the duty ratio deviation increases
Solution Approach 1:
The patent implements a feedback mechanism where the delay compensation is automatically adjusted based on the edge direction detected at each level shift unit. The control circuit monitors whether a rising or falling edge is present and dynamically selects the appropriate compensation delay (one or two series switch delays) for the adjacent inverter. This feedback-based dynamic adjustment ensures that the duty ratio accuracy is maintained while achieving the level shifting function, as the compensation adapts to the actual signal conditions.
3Device complexity
If simple level shift units are used, then the circuit complexity is low, but the operation margin is reduced due to delay mismatch
Solution Approach 1:
The patent segments the delay compensation function into distributed inverters connected to individual level shift units. Each inverter is responsible for compensating the delay of its adjacent level shift unit, creating a modular architecture. This segmentation allows the system to maintain relatively simple individual components while achieving overall delay balance through their coordinated operation. The modular structure adds minimal complexity compared to a completely redesigned level shift unit, while significantly improving the operation margin through cumulative delay compensation.
Data Source
AI summary
According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.