High-Voltage Level Shift Circuit Using Current Mirrors to Block Error Signals
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Solution Overview
Problem
Conventional high-voltage level shift circuits experience current flow issues due to parasitic inductance and capacitance, leading to error signals and malfunctions in power devices, particularly in high-potential systems like 600-V or 1200-V systems, where separate constant current sources are necessary to stabilize operation but increase heating and inefficiency.
Innovation Solution
A high-voltage level shift circuit utilizing PMOS and NMOS current mirror circuits to manage drain currents and output currents, combined with an I/V signal conversion circuit, which reduces current flow and prevents error signal transmission by maintaining high impedance states and controlling voltage levels, thereby stabilizing the operation without relying on separate constant current sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate constant current source is used to stabilize operation in high-voltage level shift circuits, then operational stability is improved, but current consumption increases and heating occurs
Solution Approach 1:
The patent removes the separate constant current source from the circuit configuration. Instead of using an external current source, the invention uses the intrinsic properties of the MOS transistors and their interconnections to provide the necessary biasing and stabilization, thereby eliminating the harmful current path while maintaining operational stability
Solution Approach 2:
The circuit uses its own internal transistor characteristics and interconnections to provide the stabilization function that previously required an external constant current source. The MOS transistors self-regulate their operation through the parasitic capacitance and diode effects, eliminating the need for separate biasing components
2Reliability
If logic filter schemes with mask signal circuits are used to prevent error signals, then malfunction prevention is improved, but device complexity increases
Solution Approach 1:
The patent removes the mask signal circuit and logic filter components from the system. Instead of adding complex filtering logic, the invention fundamentally changes the level shift circuit design to eliminate error signal generation at its source by removing the parasitic current path that causes the error signals
Solution Approach 2:
Instead of trying to detect and filter error signals after they are generated, the invention inverts the approach by designing the level shift circuit to prevent error signal generation in the first place. The solution addresses the root cause rather than the symptom
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces current consumption and prevents error signal transmission, enhancing the stability and efficiency of high-voltage level shift operations, widening the signal transmissible region and preventing unintended logical output inversions, even during high-voltage transitions.
Implementation Method 1
This causes a voltage drop and causes the error signal to be transmitted to the transmission circuit 101 at the following stage, which may induce a malfunction of the power device.
Implementation Method 2
The error signal causes a current to flow into the level shift resistors R1 and R2 connected to a high-potential side power supply via the parasitic capacitances or parasitic diodes of T1 and T2.
Data Source
AI summary
A high-voltage level shift circuit includes: a first high withstand voltage NMOS transistor driven by an on command; a second high withstand voltage NMOS transistor driven by an off command; a first PMOS current mirror circuit inputting a drain current of the first high withstand voltage NMOS transistor to a reference side; a second PMOS current mirror circuit inputting a drain current of the second high withstand voltage NMOS transistor to a reference side; a first NMOS current mirror circuit inputting an output current of the second PMOS current mirror circuit to a reference side; and an I/V signal conversion circuit receiving an output of the first PMOS current mirror circuit and an output of the first NMOS current mirror circuit to obtain an output control voltage signal.