Power Supply Circuit Using Level Shift Gate Control
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Solution Overview
Problem
Conventional power supply circuits using single and conductive-type MOS transistors suffer from voltage drop issues due to incomplete ON/OFF states of nMOS transistors, leading to decreased power efficiency and increased power consumption.
Innovation Solution
A power supply circuit is designed with a charge-pump circuit and a level shift gate control circuit to precisely control the ON/OFF states of MOS transistors, using control voltages to synchronize with voltage changes across capacitors, ensuring accurate state transitions and preventing voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a power supply circuit is made up of only single and conductive-type MOS transistors to reduce manufacturing process complexity, then the number of impurity implantation processes is reduced, but power consumption increases and voltage drop occurs due to incomplete ON/OFF states
Solution Approach 1:
A level shift circuit is introduced as an intermediary component between the clock signal source and the charge pump circuit. This level shift circuit generates control voltages with extended amplitude ranges that properly turn ON and OFF the MOS transistors in the charge pump, eliminating the voltage drop issue while maintaining the single-type transistor architecture's manufacturing simplicity
Solution Approach 2:
The control voltage amplitude parameter is changed and extended by the level shift circuit. Instead of using standard clock voltage levels, the level shift circuit produces control voltages with amplitudes that exceed the MOS transistor threshold voltages, ensuring complete switching states and preventing power loss
2Device complexity
If single and conductive-type MOS transistors are used to simplify the circuit structure, then device complexity is reduced, but the noise margin and output margin decrease
Solution Approach 1:
The control voltage amplitude is increased through the level shift circuit, creating larger voltage swings that provide greater noise margin. The extended amplitude ensures that MOS transistors switch completely between ON and OFF states, increasing the tolerance to noise and improving circuit reliability
3Reliability
If the clock voltage amplitude is increased to improve MOS transistor switching, then the ON/OFF states become more distinct, but voltage drops occur due to insufficient gate control voltage levels
Solution Approach 1:
The level shift circuit acts as a mediator that receives the clock signal and transforms it into control voltages with appropriate amplitude levels. This intermediary ensures that MOS transistor gates receive sufficient voltage to completely turn ON and OFF, preventing voltage drops while maintaining distinct switching states
Solution Approach 2:
The control voltage amplitude parameter is transformed and extended by the level shift circuit. The circuit generates control voltages with amplitudes that are specifically tailored to exceed the MOS transistor threshold voltages, ensuring complete switching without voltage drop
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively maintains the ON/OFF states of MOS transistors, preventing voltage drops and reducing power consumption, thereby enhancing the efficiency and stability of the power supply circuit.
Implementation Method 1
a charge-pump circuit including at least one MOS transistor and at least one capacitor, to charge the at least one capacitor to a charging voltage by applying a specified DC input voltage through the at least one MOS transistor
Data Source
AI summary
A power supply circuit is provided which is capable of preventing a drop in an output voltage of the power supply circuit used as a DC/DC converter made up of single and conductive type (n-type or p-type) MOS transistors and of improving efficiency. Since a control voltage having an amplitude [2×VDD] is applied from a level shift circuit to a charge-pump circuit, even when potentials at nodes becomes a level [2×VDD], pMOS transistors are kept in an OFF state, thereby preventing leakage of currents from pMOS transistors. This avoids a drop in an DC output voltage. As inputs to the level shift circuits, potentials at nodes of the charge-pump circuit are used and, therefore, even if potentials at nodes of the level shift circuits are high, pMOS transistors are kept in an OFF state.