Level Shift Circuit Gate Potential Conversion for MOSFET Reliability
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Solution Overview
Problem
Conventional level shift circuits face challenges in minimizing the drain-to-source voltage of transistors when outputting high amplitude signals, leading to potential gate oxide layer damage and increased hot carrier degradation, especially when using low withstand voltage transistors.
Innovation Solution
A semiconductor device with a level shift circuit that includes a series coupling circuit, a first and second gate control circuit, and a potential conversion circuit, where the potential conversion circuit supplies a lower potential than the first power supply but higher than the reference power supply to the gate of an N-channel MOS transistor, reducing the drain-to-source voltage and preventing excessive voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a transistor with low withstand voltage structure is used to output high amplitude signals, then the device complexity is reduced, but the drain-to-source voltage exceeds the transistor's withstand voltage causing gate oxide layer damage and hot carrier degradation
Solution Approach 1:
The patent introduces a potential conversion circuit as an intermediary between the gate control circuit and the series coupling circuit. This circuit converts the gate potential to an appropriate level, ensuring that the drain-to-source voltage of each transistor remains within its withstand voltage range while still enabling high amplitude signal output. The potential conversion circuit acts as a mediator that reconciles the conflict between using simple low-withstand-voltage transistors and maintaining their reliability.
Solution Approach 2:
The patent changes the gate potential parameter through the potential conversion circuit. By converting the gate potential to a level that is lower than the first power supply potential but higher than the reference power supply potential, the drain-to-source voltage of each transistor is controlled to remain below its withstand voltage threshold. This parameter change allows the use of simple low-withstand-voltage transistor structures while preventing gate oxide layer damage and hot carrier degradation.
2Productivity
If conventional level shift circuit configuration is used, then the circuit can output high amplitude signals, but the drain-to-source voltage of transistors becomes excessive causing gate oxide layer damage
Solution Approach 1:
The potential conversion circuit serves as an intermediary that modifies the gate potential before it reaches the series coupling circuit. This intermediary circuit ensures that while high amplitude signals can be output, the drain-to-source voltage across each transistor is limited to safe levels, preventing gate oxide layer damage and hot carrier degradation.
Solution Approach 2:
The patent applies parameter changes by converting the gate potential to an optimized level. The potential conversion circuit transforms the gate potential to be lower than the first power supply potential but higher than the reference power supply potential, which directly controls the drain-to-source voltage to prevent excessive voltage stress on the transistor gate oxide layer while maintaining high amplitude signal output capability.
Data Source
AI summary
A semiconductor device includes: a semiconductor chip including a level shift circuit to output a high amplitude signal from an input of a logical signal, the level shift circuit including a series coupling circuit coupled to a second power supply, a control circuit coupled to the series coupling circuit for controlling the series coupling circuit based on the logical signal, and a first potential conversion circuit coupled between the series coupling circuit and the control circuit and coupled to a first power supply. The series coupling circuit includes a plurality of first MOS transistors coupled in series between the second power supply and a reference power supply, and a plurality of second MOS transistors coupled in series between the second power supply and the reference power supply in series with the plurality of first MOS transistors.