Level Shift Latch Circuitry for Retention and Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional circuit designs for memory applications are inefficient and consume a large area due to their power-up sequence, which can lead to excessive leakage and unnecessary retention states, especially when dealing with core and periphery voltage management in retention mode.
Innovation Solution
The implementation of level shift latch circuitry and power-on-reset (POR) circuitry allows for flexible power-up and power-down sequences by ensuring one power supply is fully ramped-up before another, preventing DC paths and maintaining retention signals across voltage domains, thereby optimizing power management and reducing area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional power-up sequences are used to manage core and periphery voltage, then voltage domain management is achieved, but excessive leakage and unnecessary retention states occur
Solution Approach 1:
The level shift latch circuitry is configured to preliminarily establish the correct retention state before voltage transitions occur. The circuit proactively sets the retention state based on anticipated power-up sequences, preventing leakage issues before they arise rather than reacting to them afterward.
Solution Approach 2:
The level shift latch circuitry acts as an intermediary between different voltage domains (first and second voltage domains). It mediates the interaction between these domains during power-up and power-down sequences, ensuring proper signal level translation and retention state management while preventing direct DC paths between voltage domains.
2Area of stationary object
If conventional circuit designs are used for retention mode, then voltage domain management is achieved, but large area consumption occurs
Solution Approach 1:
The circuit merges multiple functions into a single level shift latch structure. It simultaneously performs level shifting between voltage domains, latch functionality for retention state management, and power-up sequence control. This consolidation reduces the overall area compared to using separate dedicated circuits for each function.
Solution Approach 2:
The level shift latch circuitry is designed with multi-functionality to handle various power-up sequences, power-down sequences, and retention mode operations within a single circuit structure. This universal design approach eliminates the need for multiple specialized circuits, thereby reducing total area consumption while maintaining the ability to manage complex voltage domain scenarios.
3Productivity
If flexible power-up and power-down sequences are implemented, then power management efficiency is improved, but circuit complexity increases
Solution Approach 1:
The circuit is designed with dynamic capabilities to adapt to different power-up and power-down sequences. The level shift latch circuitry can respond to various voltage transition scenarios and adjust its behavior accordingly, enabling flexible power management. This dynamic design allows the circuit to handle multiple operating modes without requiring separate dedicated circuits for each scenario.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.