Current-Limited Level Shift Circuit With Selectable Multi-Output Pairs
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Solution Overview
Problem
Conventional level shift circuits experience high power consumption due to large current during state transitions and have limited applications due to only providing a single type of output signal.
Innovation Solution
A current-limited level shift circuit with multiple output terminals, utilizing PMOS and NMOS transistors along with current-limiting units to manage current flow and provide multiple output pairs for selective connection to a second stage circuit, thereby reducing power consumption and expanding application possibilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional level shift circuit is used, then signal level conversion is achieved, but large current during state transition increases power consumption
Solution Approach 1:
The patent divides the level shift circuit into multiple independent output pairs (first output pair, second output pair, third output pair), each capable of operating independently. This segmentation allows the circuit to serve multiple functions simultaneously while managing current distribution across different output paths, thereby reducing the peak current demand on any single transition path.
Solution Approach 2:
The circuit provides three pairs of output terminals that can be selectively connected to different second stage circuits based on application requirements. This multi-functionality allows a single circuit to replace multiple conventional level shift circuits, reducing overall power consumption while providing versatile output options for different load requirements.
2Adaptability or versatility
If conventional level shift circuit with single output is used, then circuit structure is simple, but application scope is limited
Solution Approach 1:
The patent implements a level shift circuit with three pairs of output terminals (first, second, and third output pairs), where each pair can be selectively connected to different second stage circuits. This multi-functional design enables the circuit to adapt to various application scenarios including driving different types of logic circuits, providing both complementary and non-complementary output signals, and supporting multiple voltage level conversions simultaneously, thereby significantly expanding application scope while maintaining a unified circuit architecture.
Solution Approach 2:
The circuit is divided into multiple output pairs with independent control capabilities, allowing each output pair to be configured for specific application requirements. This segmentation provides flexibility in connecting to different second stage circuits while maintaining a relatively compact overall structure, balancing complexity and versatility.
Data Source
AI summary
A current-limited level shift circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first current-limiting unit, a second current-limiting unit, a first NMOS transistor and a second NMOS transistor, for providing a pair of input terminals and three pairs of output terminals outputting level shift signals. The first current-limiting unit is connected between the third output terminal and the fifth output terminal, and the second current-limiting unit is connected between the fourth output terminal and the sixth output terminal, for providing the current limiting of state transition. The pair of the first output terminal and the second output terminal, the pair of the third output terminal and the fourth output terminal, and the pair of the fifth output terminal and the sixth output terminal are selectively for providing multiple choices to the second stage.