Level Shift Power Semiconductor Device Isolation
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Solution Overview
Problem
High voltage integrated circuits (HVICs) face challenges in maintaining high breakdown voltage while minimizing on-resistance and preventing cross-talk between high voltage and low voltage units, particularly due to the limitations of lateral diffusion MOS (LDMOS) transistors in level shift devices.
Innovation Solution
A power semiconductor device design that includes a semiconductor substrate with a high voltage unit, a low voltage unit, and a level shift unit, where the level shift unit is electrically isolated from both units using vertically aligned isolation regions, and incorporates a drain drift region with a reduced surface field (RESURF) structure to enhance breakdown voltage and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If LDMOS transistors are used for level shift devices in the junction termination region, then the device can perform signal level shifting between high voltage and low voltage units, but cross-talk between high voltage and low voltage units occurs and reliability is reduced
Solution Approach 1:
The junction termination region is segmented into multiple isolated regions: a first isolation region separating the high voltage unit from the level shift device, and a second isolation region separating the low voltage unit from the level shift device. This segmentation creates electrical isolation barriers that prevent cross-talk while maintaining the level shifting function.
Solution Approach 2:
Isolation regions are introduced as intermediary structures between the high voltage unit, level shift device, and low voltage unit. These intermediary regions act as electrical barriers that prevent direct interaction and cross-talk between adjacent units while allowing the level shift device to perform its signal conditioning function.
2Strength
If the breakdown voltage is increased to handle high voltage signals, then the device can operate at higher voltages, but the on-resistance increases which reduces efficiency
Solution Approach 1:
Different regions of the semiconductor device are assigned different doping concentrations and structures optimized for their specific functions: the drift region is designed with specific doping to achieve high breakdown voltage, while the channel and source/drain regions are optimized for low on-resistance. This local optimization allows simultaneous achievement of high breakdown voltage and low on-resistance.
Solution Approach 2:
The device parameters such as doping concentration, layer thickness, and junction depth are carefully adjusted to achieve the optimal balance between breakdown voltage and on-resistance. By changing these parameters in the drift region and channel region, the device can maintain high breakdown voltage while minimizing on-resistance losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents cross-talk and improves breakdown voltage, maintaining high reliability and efficiency in power semiconductor devices by electrically isolating the level shift devices from high voltage units and dispersing electric fields efficiently.
Implementation Method 1
a first isolation region of a first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit
Implementation Method 2
By using a reduced surface field (RESURF) technique, a high breakdown voltage may be obtained while an LDMOS transistor has a low on-resistance
Data Source
AI summary
In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.