Level Shift Circuit Power Sequencing for Predictable Outputs
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Solution Overview
Problem
Traditional level shift circuits experience unpredictable output voltage levels when the high voltage supply is enabled while the low voltage supply is disabled, leading to potential high current conditions on common buses, especially when controlling tri-state output buffers.
Innovation Solution
A level shift circuit design incorporating a first control circuit with NMOS and PMOS transistors, where the control circuit forces the output to a known voltage when enabled and disconnects the PMOS transistor from the high voltage supply when disabled, ensuring stable and predictable voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the high voltage supply is enabled while the low voltage supply is disabled, then the level shift circuit can operate with only high voltage power, but the output voltage levels become unpredictable and may cause high current conditions
Solution Approach 1:
The control circuit monitors the power supply status and proactively forces the output to a known voltage state before the level shift circuit operates. When the low voltage supply is disabled, the control circuit detects this condition and preemptively sets the output to a defined voltage level, preventing unpredictable behavior before it occurs.
Solution Approach 2:
A control circuit acts as an intermediary between the power supply system and the level shift circuit. This control circuit includes transistors that monitor power supply status and intervene to force the output to a known voltage when abnormal power conditions are detected, mediating between the power supply flexibility requirement and output stability requirement.
2Reliability
If the control circuit continuously monitors power supply status, then output voltage stability is improved, but power consumption increases due to additional active components
Solution Approach 1:
The control circuit does not continuously monitor power supply status but instead uses periodic or event-driven monitoring. The control transistors are activated only when power supply status changes or when specific conditions are detected, allowing the circuit to consume minimal power during normal operation while still providing stability when needed.
Solution Approach 2:
The monitoring and control functions are extracted as separate control circuit components that are only actively engaged when abnormal conditions occur. During normal operation, the level shift circuit operates independently without continuous intervention from the control circuit, reducing overall power consumption while maintaining reliability.
3Reliability
If the control circuit forces the output to a known voltage using additional transistors, then output voltage stability is improved, but device complexity increases
Solution Approach 1:
The control circuit components, particularly the transistors used to force the output voltage, are designed to serve multiple functions. These transistors not only force the output to a known voltage during abnormal power conditions but also integrate with the existing level shift circuit architecture, potentially assisting in normal operation or serving as part of the overall signal transmission path.
Solution Approach 2:
The control circuit is merged with the existing level shift circuit rather than being implemented as a completely separate system. The control transistors are integrated into the circuit architecture, sharing common nodes and interacting with the existing transistor network, which reduces overall device complexity compared to a fully separate control system.
Data Source
AI summary
A level shift circuit for providing predictable outputs when VDDH is powering up and minimizing DC current when VDDL is powering up. The level shift circuit may have a control circuit that includes a first inverter with an input coupled to VDDL, one or more diodes coupled between the first inverter and its powering voltage supply, a second inverter coupled to an output of the first inverter (optionally coupled to its voltage supply via one or more diodes), a third inverter coupled to an output of the second control inverter, an NMOS transistor coupled to an output of the third inverter that forces the output of the level shift circuit to the ground voltage when enabled, and a PMOS transistor coupled to an output of the third inverter that disconnects a portion of the level shift circuit, and thus the output of the level shift circuit, from VDDH when disabled.