Level Shift Circuit With Automatic Timing for Compact High-Speed Conversion
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Solution Overview
Problem
Existing level shift circuits face challenges in converting low amplitude signals to high amplitude signals while maintaining a compact circuit area, as they require larger discharge elements, leading to increased circuit area and power consumption due to the need for high discharge capacity and charge capacity balance.
Innovation Solution
A level shift circuit configuration using complementary n-channel and p-channel MOS transistors with load elements to control gate voltages, allowing for efficient conversion of low amplitude signals to high amplitude signals without significant increases in circuit area, achieved through optimized transistor sizes and load element operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the element size of discharge elements N1 and N2 is increased to enhance discharge capability, then the discharge capacity is improved, but the circuit area increases
Solution Approach 1:
The patent introduces a capacitor as an intermediary energy storage element between the discharge elements and the output terminals. This capacitor temporarily stores discharge charge, allowing the discharge elements to be smaller while still achieving the required discharge capability. The capacitor mediates the energy transfer, decoupling the size requirements of discharge elements from the actual discharge capacity needed at the output.
Solution Approach 2:
The patent changes the operational parameters by introducing controlled timing through the capacitor charging/discharging cycles. By controlling when and how the capacitors charge and discharge, the system achieves high discharge capability during critical moments without requiring continuously large discharge elements. The parameter change involves transitioning from steady-state large element design to dynamic timing-controlled operation.
2Reliability
If the element size of charge elements P1 and P2 is increased to enhance charge capability, then the charge capacity is improved, but the circuit area increases
Solution Approach 1:
The patent uses capacitors as intermediary elements that store charge during charging phases and release it during discharge phases. This allows the charge elements P1 and P2 to be smaller in size while still achieving the required charge capacity, because the capacitors temporarily hold the charge energy. The intermediary capacitor decouples the charge element size from the actual charge delivery capability.
Solution Approach 2:
The patent implements preliminary charging action where capacitors are charged in advance during specific time windows controlled by timing signals. This preliminary charging allows the system to accumulate necessary energy before it is needed for discharge, enabling smaller charge elements to achieve the same effective charge capacity by operating at higher intensity for shorter durations during predetermined time intervals.
3Area of stationary object
If the transistor sizes are optimized to reduce circuit area, then the circuit area is reduced, but the discharge and charge capacity balance becomes difficult to maintain
Solution Approach 1:
The patent implements feedback control through timing circuits that monitor and control the charging and discharging operations of the capacitors. The timing signals ensure that charge elements and discharge elements operate in coordinated fashion, maintaining the capacity balance even with smaller transistor sizes. The feedback mechanism adjusts the timing and duration of charge/discharge cycles to compensate for the reduced transistor capacity, ensuring reliable operation.
Solution Approach 2:
The patent transitions from static transistor sizing to dynamic operation by introducing time-varying control signals that adjust the operational characteristics of the transistors and capacitors. The system dynamically switches between charging and discharging modes, with the timing and duration of each mode optimized to maintain capacity balance. This dynamic approach allows smaller transistors to achieve the required performance by operating at optimal points during specific time intervals rather than requiring continuous high capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed level shifting with low power consumption and reduced circuit area, as it balances discharge and charge capacities without requiring excessively large transistors, thus improving operational efficiency and minimizing power consumption.
Implementation Method 1
third and fourth transistors of a second conductive type which are coupled between a second supply terminal, and the first and second output terminals, respectively
Implementation Method 2
A level shift circuit configuration using complementary n-channel and p-channel MOS transistors with load elements to control gate voltages, allowing for efficient conversion of low amplitude signals to high amplitude signals
Data Source
AI summary
A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.