CMOS Level Shift Circuit With Voltage-Drop Acceleration
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Solution Overview
Problem
Existing level shift circuits face challenges in maintaining high-speed logical inversion and ensuring timing margins when the difference between power voltages increases, leading to delays and increased transistor size, which hinders integration and stability in voltage booster circuits.
Innovation Solution
A level shift circuit design that includes a first inverter for level conversion, a second inverter for operation acceleration, and a voltage dropping circuit to accelerate the change of control signals, allowing the second inverter to operate immediately and reducing the need for large transistors, thereby minimizing area and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the difference between power voltages increases, then the voltage level conversion range is improved, but the inversion speed decreases and timing margin is lost
Solution Approach 1:
The voltage dropping circuit proactively reduces the voltage level of the first control signal before it reaches the second inverter, ensuring that the second inverter can operate at high speed regardless of the power voltage difference. This preliminary voltage reduction action prevents the timing delay that would otherwise occur when the voltage difference is large.
Solution Approach 2:
The voltage dropping circuit acts as an intermediary between the first inverter and the second inverter, mediating the control signal voltage level. It transforms the high-voltage control signal from the first inverter into a lower voltage signal suitable for the second inverter, enabling high-speed operation while accommodating large voltage differences between power supplies.
2Speed
If transistor size is increased to maintain inversion speed with large voltage differences, then the inversion speed is improved, but the circuit area increases
Solution Approach 1:
The voltage dropping circuit changes the voltage parameter of the control signal to enable the second inverter to operate at high speed without requiring large transistor sizes. By reducing the control signal voltage level, the second inverter can use smaller transistors while maintaining fast switching performance, thus reducing the overall circuit area.
3Device complexity
If the voltage level of the first control signal is not dropped, then the circuit complexity is reduced, but the timing margin is insufficient and operation becomes unstable
Solution Approach 1:
The voltage dropping circuit serves as a necessary intermediary component that ensures reliable operation when large voltage differences exist between power supplies. While it adds some circuit complexity, it provides the timing margin needed for stable operation, preventing signal integrity issues and timing violations that would occur without it.
Data Source
AI summary
To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second inverters 300 and 200 of a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverter 300 is used as a level converting unit. A voltage level of a first control signal CS1 output from an output node no1 of the first inverter 300 is forcibly dropped down by a voltage dropping circuit CONT1 so as to accelerate the operation of the second inverter 200. As a result, the inversion of the level of an output signal of the first inverter 300 is accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverter 200 are reduced so as to suppress an increase in a circuit area.