Multi-Voltage Data Retention Circuit With Level-Shifter Latch Path
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Solution Overview
Problem
Existing data retention circuits face challenges in efficiently retaining data bits across power domains with different voltage levels, leading to limitations in energy conservation and circuit flexibility during power down modes.
Innovation Solution
A data retention circuit utilizing a master latch, slave latch, and retention latch operating in separate power domains with distinct voltage levels, along with a level shifter to transition logical states between these domains, enabling data retention during power down modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data bits are saved using latch circuits during power down events, then data continuity is maintained, but power consumption increases and battery life is reduced
Solution Approach 1:
The circuit is divided into a first power domain containing master and slave latches, and a second power domain containing a retention latch. This segmentation allows different portions of the circuit to operate independently with respect to power supply, enabling the retention latch to maintain data while other portions can be powered down to conserve energy.
Solution Approach 2:
A level shifter acts as an intermediary between the first power domain (VDD1) and the second power domain (VDD2). This level shifter enables communication and data transfer between domains with different voltage levels, allowing the retention latch to receive and hold data from the master latch while operating at a different voltage level.
2Reliability
If latch circuits are used to save data bits, then data is retained during power down, but circuit flexibility and placement options are limited
Solution Approach 1:
By separating the retention latch into a distinct second power domain with independent voltage control (VDD2), the circuit gains flexibility in placement and configuration. The retention latch can be positioned optimally for data retention while the master and slave latches operate independently in the first power domain.
Solution Approach 2:
The retention latch serves multiple functions: it maintains data continuity during power down events, operates at independent voltage levels for optimized performance, and provides a buffer that enables flexible circuit design and placement options within the integrated circuit.
3Adaptability or versatility
If separate power domains with different voltage levels are used, then data retention flexibility improves, but circuit complexity increases
Solution Approach 1:
The level shifter serves as a dedicated intermediary component that manages the complexity of interfacing between different power domains. By centralizing the voltage level translation function in this specific circuit element, the overall system complexity is managed more effectively than if each interface required custom solution design.
Data Source
AI summary
A circuit includes first and second power nodes having differing first and second voltage levels, and a reference node having a reference voltage level. A master latch outputs a first data bit based on a received data bit; a slave latch includes a first inverter that outputs a second data bit based on the first data bit and a second inverter that outputs an output data bit based on a selected one of the first data bit or a third data bit; a level shifter outputs the third data bit based on a fourth data bit; and a retention latch outputs the fourth data bit based on the second data bit. The first and second inverters and the level shifter are coupled between the first power node and the reference node, and the retention latch includes a plurality of transistors coupled between the second power node and the reference node.