Level-Shifted Sample-and-Hold Circuit With Fewer Clock Phases

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Solution Overview

Problem

Existing sample-and-hold circuits and multiplying digital-to-analog converters (MDACs) face challenges due to the requirement of multiple clocks, which increases implementation complexity and reduces circuit speed.

Innovation Solution

A sample-and-hold circuit and MDAC design that incorporates a level shifting circuit and switched capacitors, operating with fewer clocks, thereby simplifying the design and improving circuit speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the CLS technique is applied using three clocks (CLK1, CLKe, CLK2), then the output swing of the operational amplifier is reduced and gain is reduced, but the implementation complexity increases and circuit speed decreases

Engineering Contradiction:

Improvepower consumptionVSAvoidclock management complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent merges the estimation phase and amplification phase clock signals into a single clock signal. The level shifting circuit uses the same clock signal to control both the estimation phase (charging capacitors C3 and C4) and the amplification phase (switching SW4 to the operational amplifier output), eliminating the need for separate CLK1, CLKe, and CLK2 signals and reducing clock management complexity while maintaining the power consumption benefits of CLS

Inventive Principle:

Principle #5Merging (Combining)

2Use of energy by moving object

If the CLS technique is applied using three clocks (CLK1, CLKe, CLK2), then the output swing of the operational amplifier is reduced and gain is reduced, but the circuit speed is reduced

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent combines multiple clock phases into a single clock signal that controls both the estimation and amplification operations. This reduces the number of clock transitions and synchronization requirements, thereby improving circuit speed while maintaining the operational amplifier gain reduction and power consumption benefits of the CLS technique

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If an additional clock CLK3 is required for the sub-ADC in pipeline ADC, then the MDAC can function properly, but the implementation difficulty increases and circuit speed decreases

Engineering Contradiction:

ImproveMDAC functionalityVSAvoidclock management complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the level shifting circuit's clock signal multi-functional by using it for both the MDAC's estimation and amplification phases, and also for controlling the sub-ADC timing in pipeline ADC applications. This single clock signal replaces what would otherwise require CLK1, CLKe, CLK2, and CLK3, reducing implementation difficulty while maintaining full MDAC functionality and improving circuit speed

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution reduces the complexity of clock management and enhances the speed of the circuit, making it easier to design and implement compared to prior art.

Implementation Method 1

The level shifting circuit is coupled to the first output node, the first output terminal, the second output node, and the second output terminal and configured to level shift a voltage at the first output node and a voltage at the second output node according to at least the first input signal and the second input signal

Methodology Applied

Scientific EffectLevel shifting:

Implementation Method 2

The first SC circuit is coupled to the first input terminal, the first output terminal, and the first input node. The second SC circuit is coupled to the second input terminal, the second output terminal, and the second input node

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20250158632A1Sample-and-hold circuit and multiplying digital-to-analog converter using same

Publication Date: 2025.05.15 REALTEK SEMICON CORP

AI summary

A sample-and-hold circuit has first and second input terminals, and first and second output terminals. The first input terminal receives a first input signal, and the second input terminal receives a second input signal. The sample-and-hold circuit includes an operational amplifier, first and second switched capacitor (SC) circuits, and a level shifting circuit. The operational amplifier has first and second input nodes and first and second output nodes. The first SC circuit is coupled to the first input terminal, the first output terminal, and the first input node. The second SC circuit is coupled to the second input terminal, the second output terminal, and the second input node. The level shifting circuit is used to level shift the voltage at the first output node and the voltage at the second output node according to at least the first input signal and the second input signal.