Level-Shifted Staircases for 3D Memory Contact Via Height Control
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Solution Overview
Problem
Three-dimensional memory devices face challenges in reducing height variations in contact via structures, which affect the reliability and performance of memory arrays.
Innovation Solution
The implementation of level-shifted staircases in three-dimensional memory devices, where an alternating stack of insulating and electrically conductive layers is formed over vertically offset horizontal top surfaces, with each staircase region having a lateral extent that decreases with vertical distance from the backside surface, to create memory stack structures with a vertical semiconductor channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar contact regions are used in three-dimensional memory devices, then the manufacturing process is simpler, but height variations in contact via structures increase, affecting reliability and performance
Solution Approach 1:
The substrate surface is segmented into multiple horizontally separated top surfaces at different vertical levels, with each surface corresponding to a specific memory array region. This segmentation allows contact via structures to be formed at appropriate height levels for each region, reducing height variations and improving reliability while managing the complexity through systematic division of the substrate surface.
Solution Approach 2:
The invention transitions from a conventional two-dimensional planar contact region to a three-dimensional structure with multiple horizontally separated top surfaces at different vertical levels. This dimensional change enables contact via structures to be formed at optimized height levels for different memory array regions, effectively reducing height variations and improving device reliability.
2Manufacturing precision
If vertically offset horizontal top surfaces are formed in memory array regions, then height variations in contact via structures are reduced, but the manufacturing process complexity increases
Solution Approach 1:
The substrate is prepared in advance by forming multiple horizontally separated top surfaces at different vertical levels before subsequent processing steps. This preliminary action of creating the vertically offset surface structure enables precise formation of contact via structures at appropriate height levels, improving manufacturing precision while the systematic approach manages the overall ease of manufacture.
3Productivity
If alternating stacks of insulating and electrically conductive layers are formed over vertically offset surfaces, then memory stack structures can be optimized, but the device complexity increases
Solution Approach 1:
The alternating stacks of insulating and electrically conductive layers are formed continuously over the multiple horizontally separated top surfaces, merging the layer formation process across different vertical levels. This merging approach optimizes memory stack structure formation efficiency by using uniform processing steps while the systematic arrangement of layers manages the device complexity.
Solution Approach 2:
The alternating stack structure serves multiple functions simultaneously: it provides electrical isolation through insulating layers, creates conductive pathways through electrically conductive layers, and accommodates the vertically offset horizontal top surfaces. This multi-functionality optimizes memory stack structure formation while the integrated design manages overall device complexity.
Data Source
AI summary
A plurality of horizontal top surfaces that are vertically offset is formed on a substrate. An alternating stack of insulating layers and spacer material layers is formed and patterned to provide a plurality of staircase regions that are laterally spaced apart and overlies a respective one of the plurality of horizontal top surfaces of the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. A set of contact via cavities are formed over the electrically conductive layers.