Timing-Controlled Level Shifter for Balanced Output Transitions
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Solution Overview
Problem
Level shifter circuits face timing imbalances due to differences in PMOS and NMOS transistor operations, leading to varying output signal transition times for 0 to 1 and 1 to 0 logic transitions, which can be impractical in timing-critical applications.
Innovation Solution
A level shifter circuit with a selection circuit that chooses the node to generate the output signal based on the slowest or fastest internal node transition, ensuring consistent output signal transition times across different logic transitions, thereby equalizing the time from input to output signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional level shifter circuit is used, then signal level shifting between different voltage domains is achieved, but output signal transition times vary for different logic transitions (0 to 1 vs 1 to 0)
Solution Approach 1:
The patent implements dynamic selection of output nodes based on the transition type. The selection circuit dynamically chooses between first and second output nodes depending on whether a 0 to 1 or 1 to 0 transition is occurring, thereby optimizing transition times for each case and eliminating the timing imbalance present in conventional static level shifters.
Solution Approach 2:
The patent changes the operational parameters of the level shifter by providing different supply voltages (first and second supply voltages) to different parts of the circuit. This allows independent optimization of the timing characteristics for rising and falling edges, resolving the contradiction between reliable signal transmission and consistent transition times.
2Adaptability or versatility
If PMOS and NMOS transistors are used in the level shifter, then signal level shifting is achieved, but timing imbalance occurs between different logic transitions
Solution Approach 1:
The patent segments the level shifter circuit into multiple independent paths with separate output nodes. Each path is optimized for a specific transition type, allowing the circuit to maintain adaptability across voltage domains while achieving precise timing control for each segment, thereby resolving the manufacturing precision issue.
Solution Approach 2:
The selection circuit acts as an intermediary that mediates between the PMOS and NMOS transistor paths. It selects the appropriate output node based on the transition type, ensuring that the inherent timing differences between PMOS and NMOS operations do not result in inconsistent output transition times.
3Device complexity
If a single output node is used in the level shifter, then circuit complexity is reduced, but output signal transition times cannot be equalized
Solution Approach 1:
The patent introduces dynamic node selection to manage the complexity-time tradeoff. By dynamically selecting between multiple output nodes based on the transition type, the circuit achieves equalized transition times without requiring a single overly complex output structure, thus balancing device complexity with timing performance.
Data Source
AI summary
A level shifter circuit is disclosed. The level shifter includes an input circuit configured to receive an input signal generated using a first power supply voltage level and generate, using the first power supply voltage level, a first control signal and a second control signal using the input signal. The level shifter further includes a shifter circuit configured to generate a first shifted signal and a second shifted signal using the first control signal, the second control signal, and second power supply voltage level different than the first power supply voltage level, and a selection circuit configured to select, using a value of a previous output signal and the second power supply voltage level, one of the first shifted signal or the second shifted signal to generate a current output signal.