Bias-Controlled Level Shifter for MOS Degradation Mitigation
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Solution Overview
Problem
MOS transistors in level shifters are prone to degradation due to HCI, TDDB, and BTI, leading to instability in voltage levels and signal buffering.
Innovation Solution
A level shifter design incorporating a discharge circuit, charge supply circuit, and voltage adjustment circuit with MOS transistors that adjust voltage levels based on bias voltage, detect terminal voltages, and supply compensation currents to mitigate leakage effects, ensuring stable operation even when power supply voltages are equal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MOS transistors are used in level shifters to adjust voltage levels, then voltage level adjustment capability is improved, but transistor degradation due to HCI, TDDB, and BTI occurs leading to instability
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gate voltage of the MOS transistor through a voltage adjustment circuit. The circuit modifies the gate voltage based on detected voltage levels to optimize transistor operation and reduce stress, thereby mitigating degradation from HCI, TDDB, and BTI effects while maintaining voltage level adjustment capability.
Solution Approach 2:
The patent implements feedback through a voltage detection circuit that continuously monitors the voltage level and provides feedback to the voltage adjustment circuit. This closed-loop feedback mechanism allows the system to automatically adjust the gate voltage to maintain optimal transistor operation and prevent degradation, resolving the contradiction between adaptability and reliability.
2Reliability
If voltage adjustment circuit operates continuously to compensate for leakage current, then output voltage stability is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by enabling the voltage adjustment circuit to operate in a controlled manner rather than continuously. The circuit activates when voltage adjustment is needed and can enter low-power states when stabilization is achieved, reducing overall power consumption while maintaining output voltage stability through periodic compensation for leakage current.
Solution Approach 2:
The patent implements dynamics by making the voltage adjustment circuit's operation adaptive and conditional. The circuit dynamically adjusts its activity based on the detected voltage levels and stabilization requirements, transitioning between active adjustment modes and low-power maintenance modes to balance stability and power consumption.
3Reliability
If bias voltage is applied to adjust lower limit of output node voltage, then MOS transistor degradation is alleviated, but circuit complexity increases
Solution Approach 1:
The patent applies universality by designing the voltage adjustment circuit to perform multiple functions: it adjusts the gate voltage to set the lower limit of output voltage, compensates for leakage current, and provides feedback control. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity while achieving transistor degradation mitigation.
Solution Approach 2:
The patent implements merging by combining the voltage adjustment functionality with the leakage compensation and feedback control in a single integrated circuit block. The voltage adjustment circuit integrates multiple functions that work together to mitigate transistor degradation without requiring separate independent circuits, thus controlling the increase in device complexity.
Data Source
AI summary
A level shifter may include: a discharge circuit configured to receive an input signal on the basis of a first power supply voltage, and discharge an internal node on the basis of the input signal; a charge supply circuit configured to supply charge to an output node from which an output signal is outputted, on the basis of a second power supply voltage; and a voltage adjustment circuit including a first MOS transistor coupled between the internal node and the output node, and configured to adjust the voltage of the output node on the basis of a bias voltage applied to the first MOS transistor, and stop the operation of adjusting the voltage of the output node on the basis of the bias voltage, when the levels of the first and second power supply voltages are equal to each other.