CMOS Level Shifter Without Bias Voltage for Low-Power Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing level shifters in integrated circuits (ICs) face challenges in efficiently communicating between different power domains due to voltage stress limitations and the need for additional bias voltages, which increases power consumption.
Innovation Solution
A level shifter design that includes a NOT gate, a BJT transistor, a MOSFET transistor, and load circuits, which allows for the conversion of input signals between different supply voltages and ground voltage without requiring a bias voltage, thus reducing power consumption and improving operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional level shifters are used to convert logic levels between different power domains, then signal communication is achieved, but additional bias voltages are required which increases power consumption
Solution Approach 1:
The patent extracts and eliminates the bias voltage generation circuitry from the level shifter design. By using a differential pair configuration where the input signal directly controls the differential transistors, the need for separate bias voltage sources is removed, thereby reducing power consumption and device complexity
Solution Approach 2:
The differential pair circuit serves multiple functions simultaneously: it performs level shifting, provides differential signal processing, and eliminates the need for bias voltage generation. This multi-functionality reduces the overall power consumption and simplifies the device structure
2Reliability
If medium voltage transistors are used to withstand higher voltage stress, then voltage compatibility is improved, but the computing speed decreases compared to low voltage transistors
Solution Approach 1:
The patent applies different transistor types in different regions of the circuit: low voltage transistors are used where high speed is needed (input stage and differential pair), while the output stage handles the voltage level conversion. This local optimization allows each part of the circuit to operate at its optimal performance point
Solution Approach 2:
The patent transitions from a single-voltage-domain design to a multi-voltage-domain design by using a differential pair configuration. This allows the circuit to handle both low voltage input signals and high voltage output signals simultaneously, effectively bridging the speed-reliability trade-off by operating in different voltage dimensions
3Adaptability or versatility
If multiple level shifters are used to convert multiple control signals, then communication completeness is improved, but the device complexity and area increase
Solution Approach 1:
The patent merges multiple single-ended level shifter functions into a single differential level shifter. By using a differential pair configuration, multiple control signals can be processed simultaneously through the differential architecture, reducing the total number of level shifters needed and thereby decreasing device complexity and area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed level shifter effectively converts logic levels between different power domains without the need for additional bias voltages, reducing power consumption and enhancing operational efficiency, while being compatible with existing CMOS manufacturing processes.
Implementation Method 1
a level shifter design that includes a NOT gate, a BJT transistor, a MOSFET transistor, and load circuits, which allows for the conversion of input signals between different supply voltages and ground voltage
Implementation Method 2
A drain terminal of the MOSFET transistor is connected to an emitter of the BJT transistor. A source terminal of the MOSFET transistor receives the ground voltage. A gate terminal of the MOSFET transistor receives the input signal
Data Source
AI summary
A level shifter includes a first load circuit, a second load circuit, a BJT transistor, a first MOSFET transistor and a NOT gate. A first terminal of the first load circuit receives the second supply voltage. A first terminal of the second load circuit receives the input signal. A collector of the BJT transistor is connected with a second terminal of the first load circuit. A base of the BJT transistor is connected with a second terminal of the second load circuit. A drain terminal of the first MOSFET transistor is connected with an emitter of the BJT transistor. A source terminal of the first MOSFET transistor receives a ground voltage. A gate terminal of the first MOSFET transistor receives the input signal. An input terminal of the NOT gate is connected with the first load circuit. An output terminal of the NOT gate generates an output signal.