Level Shifter Circuit for MOS Breakdown Protection Margin
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Solution Overview
Problem
Semiconductor devices with embedded nonvolatile memory circuits face challenges in resisting high voltage stress, leading to potential gate oxide damage and operational failures due to insufficient breakdown voltage prevention in existing level shifter configurations, which reduces the overall operation margin of the semiconductor circuit.
Innovation Solution
The proposed solution involves an enhanced level shifter design that includes an exceeded-breakdown-voltage prevention circuit with additional PMOS transistors coupled in series to cross-coupled transistors, allowing for improved breakdown voltage management and reduced voltage applied to MOS transistors, thereby enhancing the resistance to high voltage stress without compromising the operation margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clamp potential supplied to the gate of each of the third and fourth PMOS transistors is increased, then the breakdown voltages of the first and second PMOS transistors are more reliably prevented from being exceeded, but the operation margin of the entire semiconductor circuit is reduced
Solution Approach 1:
The exceeded-breakdown-voltage prevention circuit is divided into multiple transistor stages (first PMOS, second PMOS, third PMOS, fourth PMOS) with different functions. The first and second PMOS transistors are dedicated to breakdown prevention with their gates coupled to the intermediate node, while the third and fourth PMOS transistors handle input signal transmission. This segmentation allows each transistor to be optimized for its specific function without compromising overall circuit operation margin.
Solution Approach 2:
An intermediate node is introduced between the latch circuit and the input circuit to mediate voltage levels. The first and second PMOS transistors are coupled between the high-potential power supply and this intermediate node, creating an intermediate voltage level that prevents breakdown while allowing the input circuit to operate with adequate margin. This intermediary structure decouples the breakdown prevention function from the signal transmission function.
2Strength
If a high voltage is applied to a MOS transistor, then the transistor can handle higher voltage stress, but the gate oxide film is damaged due to FN degradation
Solution Approach 1:
The first and second PMOS transistors are configured to activate in advance to prevent breakdown voltage from reaching the latch circuit transistors. By placing these protection transistors at the input stage and coupling their gates to the intermediate node, they create a preliminary barrier that limits voltage stress before it can damage the gate oxide of subsequent transistors.
Solution Approach 2:
The exceeded-breakdown-voltage prevention circuit acts as a cushioning layer between the high-voltage input and the sensitive latch circuit. The first and second PMOS transistors absorb and limit voltage excursions, providing beforehand protection against FN degradation and gate oxide damage in the cross-coupled transistors.
Data Source
AI summary
Provided is a level shifter which can retain an operation margin and enhance an exceeded-breakdown-voltage preventing effect. The level shifter in an embodiment includes an exceeded-breakdown-voltage prevention circuit between a pair of first-conductivity-type cross-coupled transistors and a pair of second-conductivity-type input transistors. The exceeded-breakdown-voltage prevention circuit includes first-conductivity-type first transistors and second-conductivity-type second transistors which are coupled in series to each other, and first-conductivity-type third transistors coupled in series to the first and second transistors on a higher-potential side.