Voltage-Relaxed Level Shifter for Lower Breakdown Stress
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Solution Overview
Problem
Conventional level shifters in SRAM or flash EEPROM memories face issues with high source-drain voltage, leading to increased breakdown voltage requirements, which can result in higher costs and circuit area, due to insufficient current driving ability of transistors.
Innovation Solution
A level shifter design that includes input transistors, voltage relaxing transistors, and inverter circuits to increase the rate of voltage variation at output nodes, reducing the source-drain voltage and relaxing the breakdown voltage limit by connecting transistors and reference nodes in a specific configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the current driving ability of the transistor is increased to reduce the rise time of source voltage, then the source-drain voltage decreases, but the breakdown voltage requirement increases
Solution Approach 1:
The patent introduces a voltage relaxing transistor as an intermediary component between the input transistor and the output node. This intermediary transistor actively controls the voltage at the drain node, preventing it from rising too quickly while still allowing the source voltage to rise at the required speed. The voltage relaxing transistor acts as a mediator that decouples the relationship between input signal transitions and output voltage changes, thereby reducing the source-drain voltage without compromising the rise time performance.
Solution Approach 2:
The patent changes the voltage parameters at critical nodes by introducing controlled voltage relaxation. The voltage relaxing transistor dynamically adjusts the drain voltage level based on the operating conditions, effectively changing the voltage parameters to maintain a smaller voltage difference between source and drain. This parameter change approach allows the system to operate with reduced voltage stress on transistors while maintaining signal integrity and timing requirements.
2Reliability
If a high breakdown voltage transistor is used to accommodate the maximum source-drain voltage, then the transistor can handle voltage spikes, but the circuit area and manufacturing cost increase
Solution Approach 1:
The voltage relaxing transistor serves as an intermediary that protects downstream transistors from high voltage stress. By actively controlling the drain voltage and preventing excessive voltage buildup, this intermediary component allows the use of transistors with lower breakdown voltage ratings, thereby reducing the required transistor size and overall circuit area while maintaining reliability.
Solution Approach 2:
The patent implements beforehand cushioning by proactively managing voltage levels through the voltage relaxing transistor. Before voltage spikes can damage sensitive transistors, the voltage relaxing transistor preemptively clamps or relaxes the voltage to safe levels. This prior protection mechanism eliminates the need to design for worst-case voltage scenarios, allowing the use of smaller, more cost-effective transistors with lower breakdown voltage specifications.
3Speed
If the rise time of drain voltage is made faster to match source voltage transition, then the source-drain voltage is reduced, but additional circuit complexity is introduced
Solution Approach 1:
The voltage relaxing transistor acts as a sophisticated intermediary that automatically adjusts drain voltage based on simple control signals. Rather than requiring complex feedback circuits or multiple active components to achieve fast drain voltage transition, this single intermediary transistor with appropriate biasing provides the necessary voltage control, simplifying the overall circuit architecture while achieving the desired speed performance.
Data Source
AI summary
Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.