Level Shifter Bypass Switching to Mitigate Signal Delay
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Solution Overview
Problem
Level shifters in semiconductor devices experience delays and increased power consumption due to the number of transistors involved in signal traversal and static current buildup, especially when operating in voltage domains with low gate-source voltages.
Innovation Solution
A semiconductor device design incorporating a level shifter and a switch module, where the switch controller determines the relative voltages and generates control signals to bypass the level shifter when the input voltage is higher, reducing signal delay and static current by disconnecting the level shifter from the output and connecting the input directly to the output in such cases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the level shifter is used to shift signals between voltage domains, then voltage domain compatibility is improved, but signal delay increases due to the number of transistors involved
Solution Approach 1:
The patent implements a dynamic switching mechanism that adapts the signal path based on voltage domain conditions. When the input voltage domain is higher than the output voltage domain, the switch module bypasses the level shifter to reduce delay. When voltage domain shifting is required, the level shifter is activated. This dynamic adaptation resolves the contradiction by making the system flexible rather than static.
Solution Approach 2:
The signal transmission path is segmented into multiple routes: one through the level shifter for voltage domain adaptation, and another bypass route for direct transmission when voltage adaptation is not needed. This segmentation allows the system to choose the optimal path based on conditions, reducing unnecessary delay while maintaining voltage domain compatibility when required.
2Adaptability or versatility
If the level shifter operates in voltage domains with low gate-source voltages, then voltage domain flexibility is improved, but power consumption increases due to static current buildup
Solution Approach 1:
The switch module dynamically controls the activation of the level shifter based on voltage domain comparison. When the input voltage is higher than the output voltage, the bypass path is activated and the level shifter is deactivated, eliminating static current consumption. When voltage domain shifting is required, the level shifter is activated. This dynamic control resolves the contradiction by making power consumption conditional rather than continuous.
Solution Approach 2:
The harmful static current consumption is extracted and eliminated by providing an alternative signal path that bypasses the level shifter when voltage domain shifting is not required. This separation allows the system to maintain voltage domain flexibility when needed while eliminating the energy waste associated with static current buildup in unnecessary operating conditions.
3Reliability
If the level shifter is always connected to the output, then signal level shifting capability is maintained, but device complexity increases due to continuous static current paths
Solution Approach 1:
The circuit configuration is made dynamic through the switch module that can reconfigure the signal path based on voltage domain conditions. The level shifter is connected to the output only when voltage domain shifting is required, otherwise the bypass path is used. This dynamic reconfiguration maintains signal level shifting capability when needed while simplifying the active circuit configuration by removing unnecessary static current paths.
Data Source
AI summary
A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.