Capacitor-Refreshed Level Shifter for Unsynchronized Cascoded Buffers
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Solution Overview
Problem
Existing level shifter circuits face challenges in achieving continuous mode operation and efficient voltage shifting using low-voltage devices, particularly in cascoded structures, where strict synchronization with the refreshing clock is often required.
Innovation Solution
A circuit design utilizing low-voltage PMOS transistors and NAND gates allows for continuous operation by refreshing voltages on capacitors without strict synchronization constraints, enabling efficient voltage domain changes and fast propagation of shifted voltages using low-voltage MOS components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage shifting is applied to cascoded buffers using a boosted clock, then fast shifting of the driving voltage is achieved, but strict synchronization constraints are imposed between the input signal and the refreshing clock
Solution Approach 1:
The patent divides the voltage shifting operation into two independent parts: (1) capacitor charging/discharging controlled by the input signal, and (2) capacitor voltage refreshing controlled by the clock signal. This segmentation allows the input signal and clock to operate independently without strict synchronization requirements, while still achieving fast voltage shifting through the cascoded buffer structure
Solution Approach 2:
The capacitors are pre-charged to specific voltages during a refresh phase before the actual voltage shifting operation. This preliminary action ensures that the capacitors are ready to quickly respond to input signal changes without requiring synchronization with the clock, enabling fast voltage shifting while maintaining operational simplicity
2Area of stationary object
If low-voltage devices are used up to twice their maximum voltage range, then performance and area of buffers are optimized, but the voltage range extension requires cascoded structures
Solution Approach 1:
The patent combines the voltage shifting function and buffer amplification function into a single integrated structure. The cascoded buffer simultaneously performs voltage level shifting and signal buffering, eliminating the need for separate voltage shifting circuitry and reducing overall area while managing complexity through functional integration
3Speed
If capacitor-based level shifting is used to propagate input voltage to higher voltage domain, then fast propagation time is achieved, but crossbar current occurs during level shifting
Solution Approach 1:
The patent converts the potentially harmful crossbar current into a beneficial charging current. During level shifting, the current that would normally flow through the crossbar is instead used to charge the capacitors to the appropriate voltage levels, eliminating energy loss while maintaining fast propagation speed through the capacitor-based shifting mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates continuous operation with reduced power consumption and fast voltage propagation, eliminating crossbar current and enabling level shifting without synchronization needs, thus improving performance and area efficiency.
Implementation Method 1
capacitor-based level shifter circuits... capacitors used to propagate an input voltage to an, e.g., higher voltage domain
Implementation Method 2
two p-channel metal-oxide semiconductor (PMOS) transistors... efficient voltage domain changes and a fast propagation time of shifted voltage
Data Source
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AI summary
A level-shifter circuit (10) receives one or more input signals (IN; LS) in an input level domain and provides at an output node an output signal (OUT; OUT_S) in an output level domain shifted with respect to the input level domain. The circuit (10) comprises output circuitry (MPA, MPB, MPCASC, MNCASC, MNO) including a first drive node (A) and a second drive node (B) that receive first (PhaseACond) and second (PhaseBCond) logical signals so that the output signal (OUT) has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals (PhaseACond, PhaseBCond). The circuit comprises first (CSHIFTL) and second (CSHIFTR) shift capacitors coupled to the first (A) and second (B) drive nodes as well as capacitor refresh circuitry comprising a first, resp. second, refresh transistor (MPS_A resp. MPS_B) with first, resp. second refresh current flow paths therethrough between a supply node (VX) and the first (CSHIFTL) resp. second (CSHIFTR) shift capacitor via the first (A) resp. second (B) drive node. The refresh current flow paths are configured to become conductive in response to a respective refresh signal (PhaseA_S, resp. PhaseB_S) applied to the control terminal of the respective refresh transistor (MPS_A, resp. MPS_B) as well as logic circuitry (100A, 100B) configured to facilitate charge of the shift capacitors (CSHIFTL resp. CSHIFTR) via the refresh current flow paths in response to shifted refresh signals (PhaseALV; PhaseBLV) that are shifted with respect to the refresh signals (PhaseA_S resp. PhaseB_S) applied to the control terminal of the respective refresh transistor (MPS_A, resp. MPS_B).