Level Shifter IC Clock Signal Buffering for Power Reduction
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Solution Overview
Problem
Existing display devices face increased power consumption and electromagnetic interference due to successive signal transitions from the timing controller to the level shifter IC, particularly in OLED displays, which require multiple pairs of on and off clocks for generating scan, sense, and carry clocks.
Innovation Solution
The display device incorporates a level shifter IC with a scan clock generator, sense clock generator, and carry clock generator that buffer and logically process on and off clocks, allowing the timing controller to stop transmitting these signals when a previous data rewrite control signal is enabled, thereby minimizing signal transitions and reducing power consumption and EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the timing controller transmits multiple pairs of on clocks and off clocks to the level shifter IC for generating scan, sense, and carry clocks, then the gate driver can be properly controlled, but power consumption increases and electromagnetic interference increases
Solution Approach 1:
The patent combines multiple clock signal functions into a single on clock signal by encoding different clock types (scan clock, sense clock, carry clock) within the same signal line using different timing intervals. This merging approach reduces the number of separate signal transmissions from the timing controller to the level shifter IC, thereby reducing power consumption and electromagnetic interference while maintaining proper gate driver control.
Solution Approach 2:
The on clock signal is designed to serve multiple functions simultaneously. By controlling the timing intervals and using different edge transitions (rising/falling edges), a single on clock signal generates multiple types of clock signals needed for the gate driver operation. This multi-functionality eliminates the need for separate dedicated clock signal lines for each function.
2Reliability
If the timing controller transmits multiple pairs of on clocks and off clocks to the level shifter IC, then all necessary clock signals can be generated, but electromagnetic interference increases
Solution Approach 1:
Multiple clock signal functions are merged into a single on clock signal transmission. The level shifter IC internally generates the different clock types (scan, sense, carry) by processing the single on clock signal with different timing intervals and edge transitions, thereby reducing the number of signal lines and minimizing electromagnetic interference.
Solution Approach 2:
The level shifter IC acts as an intermediary that receives the single on clock signal from the timing controller and internally generates all necessary clock signals. This intermediary approach allows the timing controller to transmit fewer signals while still achieving complete clock signal generation, thereby reducing electromagnetic interference on the transmission lines.
3Reliability
If successive signal transitions are used to transmit on clocks and off clocks, then the clock signals can be transmitted reliably, but power consumption increases
Solution Approach 1:
The patent uses periodic action by controlling the timing intervals between rising and falling edges of the on clock signal to encode different clock types. Instead of using separate successive transitions for each clock type, the system uses periodic timing intervals within a single signal stream to differentiate between scan, sense, and carry clocks, reducing the total number of transitions and power consumption.
Data Source
AI summary
A display device can include a gate driver configured to drive gate lines of a panel; a data driver configured to drive data lines of the panel; a timing controller configured to control operations of the gate driver and the data driver; and a level shifter integrated circuit (IC) configured to receive a plurality of control signals from the timing controller, and generate and output a plurality gate control signals for controlling driving of the gate driver, in which the plurality of control signals include an on clock and an off clock, and the level shifter IC stores the on clock and the off clock in buffers based on one or more control signals from the timing controller, generates a plurality of scan clocks by logically processing the on clock and the off clock, and outputs the plurality of scan clocks to the gate driver.