Level Shifter Clock Signal Control for Display Panel
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Solution Overview
Problem
Conventional display devices face issues with image quality due to insufficient charging in sub-pixels and characteristic variations in gate signals, leading to deteriorated image quality and malfunctioning gate driving.
Innovation Solution
A level shifter and display device design that controls the rising and falling characteristics of clock signals, utilizing a clock control circuit to manage the on-resistance of switches and gate pulse modulation switches, allowing for independent control of clock signals to reduce characteristic variations and improve image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate driving circuit is disposed on the display panel in a panel built-in type, then the non-display area can be reduced, but the arrangement area of the gate driving circuit becomes constrained and characteristic variation between gate signals increases
Solution Approach 1:
The patent applies local quality by providing different rising lengths and falling lengths to different clock signals (first clock signal vs. second clock signal) based on their specific functions in driving different gate lines. This allows each clock signal to be optimized for its particular timing requirements, reducing characteristic variation and improving manufacturing precision while maintaining a compact panel built-in structure.
2Productivity
If clock signals are used to drive gate lines, then the display device can operate, but characteristic variation between clock signals causes image quality deterioration
Solution Approach 1:
The patent differentiates the characteristics of different clock signals by providing distinct rising lengths and falling lengths tailored to each signal's specific driving function. This localized optimization ensures that each clock signal achieves the precise timing characteristics needed for its designated gate lines, maintaining display operation while minimizing characteristic variation that would otherwise deteriorate image quality.
Solution Approach 2:
The patent changes the temporal parameters (rising length and falling length) of the clock signals to optimize their performance. By adjusting these parameters differently for the first and second clock signals, the system achieves precise timing control that reduces characteristic variation and improves image quality while maintaining productive display operation.
3Manufacturing precision
If the rising length or falling length of clock signals is extended, then characteristic variation is reduced, but the charging time in sub-pixels becomes insufficient
Solution Approach 1:
The patent applies local quality by providing different rising lengths and falling lengths to different clock signals based on their specific functions. This allows optimized timing characteristics for each signal while maintaining sufficient charging time in sub-pixels, as each signal's duration is tailored to its specific driving requirements rather than using a uniform extended duration for all signals.
Data Source
AI summary
Embodiments of the present disclosure relate to a level shifter and a display device capable of differently controlling a signal waveform between a first clock signal and a second clock signal used to output a first gate signal and a second gate signal. Accordingly, it is possible to reduce the variation in output characteristics between the first gate signal and the second gate signal, thereby improving image quality.