Level Shifter Clock Synchronization for Over-Current Detection
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Solution Overview
Problem
Display devices face challenges with accurately detecting over-currents due to deviations in time points, leading to potential damage, and the number of input signals for level shifters increases, complicating the design.
Innovation Solution
A display device design that includes a timing controller generating on-clock and off-clock signals, a level shifter generating synchronized gate clock signals with rising and falling edges, an over-current detector sensing currents at specific edges to detect over-currents, and a voltage generator stopping gate driving voltage when an over-current is detected, reducing the number of input signals and improving detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of input signals of the level shifter increases, then the functionality of the level shifter is improved, but the size of the level shifter increases
Solution Approach 1:
The patent merges multiple input signals (on-clock signal and off-clock signal) into a unified clocking mechanism for generating gate clock signals. By combining the functionality of multiple separate clock inputs into a single integrated system that generates both rising and falling edges from synchronized clock signals, the level shifter reduces its input terminal count while maintaining comprehensive clocking control for all gate signals.
2Productivity
If the over-current detector senses current at arbitrary time points, then the detection coverage is improved, but the detection accuracy deteriorates due to time deviation
Solution Approach 1:
The patent implements preliminary synchronization by aligning the current sensing operation with specific phases of the clock signal cycle. The over-current detector is configured to sense current at predetermined time points that correspond to specific edges or phases of the gate clock signals, ensuring that detection occurs at consistent, optimized moments that maximize accuracy while maintaining comprehensive monitoring coverage.
3Adaptability or versatility
If the level shifter generates gate clock signals with more input terminals, then the signal control capability is improved, but the device complexity increases
Solution Approach 1:
The patent implements a universal clocking mechanism where the level shifter uses a common on-clock signal and off-clock signal pair to control all gate clock signal generations. This multi-functional approach allows the same clock signal pair to synchronize multiple output channels (first gate clock signal, second gate clock signal, etc.), eliminating the need for separate dedicated clock inputs for each channel and thereby reducing overall device complexity while maintaining comprehensive control capability.
Data Source
AI summary
A display device may include a timing controller which generates on-clock and off-clock signals, a level shifter which sequentially generates gate clock signals each having a rising edge and a falling edge respectively synchronized with a rising edge of the on-clock signal and a falling edge of the off-clock signal, the gate clock signals having a voltage corresponding to a gate driving voltage, a gate driver generating gate signals based on the gate clock signals, an over-current detector detecting an over-current by sensing a current of each of the gate clock signals at a time point when the falling edge of the on-clock signal is generated in an on-current detection mode, and generates a shutdown signal in response to the detected over-current, and a voltage generator providing the gate driving voltage to the level shifter and stops providing the gate driving voltage in response to the generated shutdown signal.