Level Shifter With Common N-Well Biasing for Compact Isolation

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Solution Overview

Problem

Integrated circuits with multiple power domains face challenges in efficiently shifting logical levels between different power supply voltage levels, often requiring multiple transistors and separate n-wells, which can lead to increased space requirements and latch-up risks.

Innovation Solution

A level shifting circuit with a bias circuit that biases a common n-well based on the greater of two power supply voltage levels, using PMOS transistors positioned in the common n-well to avoid latch-up risks while reducing space requirements by eliminating the need for separate n-well spacing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate n-wells are used for PMOS transistors in different power domains, then latch-up risks are reduced, but space requirements increase

Engineering Contradiction:

Improvelatch-up riskVSAvoidspace requirement

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple separate n-wells into a single common n-well that hosts PMOS transistors from different power domains. This consolidation eliminates the need for spatial separation while implementing latch-up prevention through alternative means (isolated bulk connections), thereby reducing the overall area occupied by the level shifter circuit.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an intermediary structure (the common n-well with isolated bulk connections) that mediates between the conflicting requirements of having separate n-wells for latch-up prevention and using a compact layout. The bulk connections act as intermediaries to provide electrical isolation equivalent to physical separation, enabling area reduction without sacrificing reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple PMOS transistors are used for level shifting between power domains, then logical level shifting capability is achieved, but device complexity increases

Engineering Contradiction:

Improvelogical level shifting capabilityVSAvoidtransistor count

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent makes the common n-well structure universal by designing it to accommodate PMOS transistors from multiple power domains simultaneously. This multi-functional n-well configuration allows the same structural framework to handle level shifting between different voltage domains, reducing overall device complexity compared to implementing separate structures for each power domain transition.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11831310B2Level shifting circuit and method

Publication Date: 2023.11.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.