Level Shifter Current Extraction for Faster Power Transistor Turn-Off
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Low power circuits face challenges in interfacing with high power devices due to propagation delays caused by parasitic capacitances in power transistors, leading to undesired electromagnetic interference and inefficiencies.
Innovation Solution
A level shifter with a current extractor is used to control the slew rate of power transistors by selectively extracting current from the gate, reducing propagation delays through a low impedance path formed by a PMOS transistor and an NMOS current sink, while maintaining the desired slew rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a level shifter is used to interface low power circuits with high power devices, then voltage level conversion is achieved, but propagation delay increases due to parasitic capacitances in power transistors
Solution Approach 1:
The patent extracts the problematic parasitic capacitance from the gate node by adding a dedicated discharge path through the current extractor circuit. This separate extraction path allows the parasitic capacitance to be discharged independently from the normal signal path, thereby reducing propagation delay while maintaining the level shifting function.
Solution Approach 2:
The patent introduces an intermediary current extractor circuit between the level shifter output and the power transistor gate. This intermediary component provides a controlled discharge path for the parasitic capacitance, mediating between the low voltage control signal and the high voltage power transistor, thus reducing delay without compromising interface compatibility.
2Speed
If the power transistor is turned off quickly to reduce propagation delay, then switching speed improves, but electromagnetic interference increases due to sharp signal edges
Solution Approach 1:
The patent implements dynamic control of the discharge path impedance. The current extractor is configured to provide low impedance during the discharge phase to enable fast switching, then transitions to high impedance to prevent EMI during steady state. This dynamic impedance adjustment allows the circuit to achieve both fast switching speed and low EMI emission.
Solution Approach 2:
The patent employs periodic or pulsed activation of the current extractor discharge path. Rather than continuously discharging the parasitic capacitance, the circuit activates the discharge path only during the transition phase when fast switching is needed, then deactivates it to prevent continuous EMI generation, thus achieving periodic action that balances speed and EMI reduction.
Data Source
AI summary
Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level shifter to selectively turn a first circuit on and off; a first switch to couple the first circuit to a second circuit when the first circuit is on, wherein the second circuit is to selectively receive a first current from the first circuit based on a signal the second circuit receives from the level shifter; and a second switch to couple the first circuit to a reference signal based on the first current, the second switch causing the first circuit to start to turn off.