Level Shifter Circuit Structure for Balanced Rise and Fall Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face challenges with increased power dissipation and malfunction due to smaller transistor sizes, voltage domain differences, and inefficiencies introduced by level shifter circuits, which lead to delays, power consumption, and potential failures from temperature and process variations.
Innovation Solution
A level shifter circuit design with a first set of sequentially coupled pull-up and pull-down sub-circuits cross-coupled to a second set to generate a positive feedback loop, featuring an output node connected to a common node through an inverter, and NMOS transistors configured to reduce falling and rising path delays, power dissipation, and duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a level shifter circuit is used to couple different voltage domains, then voltage translation is achieved, but additional delay is introduced in signal paths
Solution Approach 1:
The level shifter circuit is divided into two separate circuits: a first level shifter circuit for translating signals from first voltage domain to second voltage domain, and a second level shifter circuit for translating signals from second voltage domain to first voltage domain. This segmentation allows each circuit to be optimized for its specific direction of operation, reducing overall signal path delay while maintaining voltage domain compatibility.
2Productivity
If transistor physical size is reduced to increase integration density, then more transistors fit on chip, but power dissipation per unit area increases causing overheating
Solution Approach 1:
The circuit is segmented into multiple voltage domains with separate level shifter circuits for each domain boundary. This allows power management at the domain level, where critical circuits can operate at higher voltages for performance while non-critical circuits operate at lower voltages to reduce power dissipation per unit area, preventing overheating while maintaining high integration density.
3Loss of energy
If supply voltage is reduced to decrease power dissipation, then power consumption decreases, but circuit speed decreases due to slower transistor switching
Solution Approach 1:
The integrated circuit is divided into multiple voltage domains where speed-critical circuit domains operate at higher supply voltages to maintain fast switching speeds, while non-speed critical circuit domains operate at lower supply voltages to reduce power dissipation. Level shifter circuits couple these domains, enabling the system to achieve both low power consumption and high speed performance simultaneously.
4Adaptability or versatility
If conventional level shifter circuit is used, then voltage domain coupling is achieved, but duty cycle distortion occurs due to unequal fall and rise path delays
Solution Approach 1:
The level shifter is segmented into two separate circuits operating in opposite directions. By designing each circuit independently and using symmetric transistor sizing techniques, the fall path delay in one circuit matches the rise path delay in the other circuit, thereby balancing the overall duty cycle and eliminating distortion while maintaining voltage domain coupling.
Data Source
AI summary
A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.