Automated Level Shifter Detection in IC Power Domains
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Solution Overview
Problem
Existing automated tools for integrated circuit design fail to detect level shifter problems effectively, especially when voltage differences between power domains are small, leading to potential digital signal transfer failures and performance issues in real-world implementations despite passing computer simulations.
Innovation Solution
An automated method using logical and topological approaches to identify level shifters within complex integrated circuit designs by analyzing cross-coupled PFET and NFET devices, tracing pathways, and determining parallel and cross-coupled stacks to mark and link level shifter components, providing a more accurate detection of level shifter circuits and their placement within power domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If computer simulations are used to verify circuit design, then design verification is automated, but level shifter problems are not detected when voltage differences are small
Solution Approach 1:
The verification process is segmented into two independent phases: (1) computer simulation for general circuit verification, and (2) topological analysis specifically for level shifter detection. This segmentation allows each phase to specialize in its strength, with the topological analysis phase specifically targeting level shifter problems that simulations miss.
Solution Approach 2:
A new intermediary verification layer is introduced between the circuit design and simulation stages. This intermediary layer performs topological analysis to identify level shifters and their connections before simulation, acting as a mediator that catches problems simulations would miss due to small voltage differences.
2Productivity
If automated tools are used to analyze circuits, then analysis efficiency is improved, but detection of level shifter errors remains insufficient
Solution Approach 1:
The patent replaces simulation-based verification (which relies on numerical calculations and electrical characteristics) with topological analysis (which relies on circuit structure and connectivity). This substitution enables automated detection of level shifters based on their topological signature rather than electrical behavior, achieving both efficiency and precision.
Solution Approach 2:
The verification approach changes from using electrical parameters (voltage, current) to topological parameters (connection structure, signal flow paths). This parameter transformation allows automated tools to detect level shifters based on their structural characteristics rather than electrical measurements, improving detection precision.
3Adaptability or versatility
If circuit complexity increases, then more functionality is achieved, but detection of design errors becomes more difficult
Solution Approach 1:
The patent extracts the level shifter detection function from the general circuit analysis. By identifying and isolating level shifter components and their connections through topological analysis, the system can verify these critical elements independently, making error detection easier even in complex circuits with many components.
Solution Approach 2:
The topological analysis is performed as a preliminary verification step before simulation. This preliminary action identifies level shifters and their connections in advance, allowing designers to address potential issues before they manifest in complex circuit operation, thereby reducing the difficulty of error detection.
Data Source
AI summary
A logical and topological based software method of detecting level shifter circuits in complex integrated circuit designs. The method, which identifies level shifters by various design rules such as suitably connected PFET and NFET pairs in various circuit contexts, rather than prior art simulation methods, can identify and mark various devices and circuits as being part of a level shifter, and also place the identified level shifters within the context of the integrated circuit chip's various power domains. In some embodiments, the method, working with little or no a-priori information other than the integrated circuit's netlist computer file, can automatically trace power and signal lines, automatically determine power domains, and automatically flag when signal lines between different power domains are not adequately protected by level shifters.