Level Shifter Circuit for Low-Voltage Display Driver Signals
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Solution Overview
Problem
The amplitude voltage of the clock signal in driver circuits for display devices, such as liquid crystal televisions, is typically the same as the gate signal, leading to high power consumption due to the high drive voltage required.
Innovation Solution
A semiconductor device with a specific configuration of transistors is used to reduce the drive voltage of the driver circuit, achieving low power consumption by increasing the amplitude voltage of output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amplitude voltage of the clock signal is set to the same level as the gate signal, then the driver circuit can drive the scan lines effectively, but the power consumption increases due to the high drive voltage
Solution Approach 1:
The circuit is divided into multiple transistor stages (first transistor for clock signal input, second transistor for signal transformation, third transistor for output) that work sequentially to transform the clock signal from high voltage to low voltage while maintaining driving capability. This segmentation allows voltage reduction without sacrificing scan line driving effectiveness.
Solution Approach 2:
The circuit transforms the voltage parameter of the clock signal through transistor switching operations. The first transistor receives a high-voltage clock signal, and through the switching action of multiple transistors controlled by gate signals, the output clock signal has a reduced voltage amplitude that is suitable for low power consumption while still maintaining the necessary driving capability for scan lines.
2Use of energy by moving object
If the drive voltage is reduced to lower power consumption, then energy efficiency improves, but the amplitude voltage of output signals may become insufficient for proper signal transmission
Solution Approach 1:
The circuit performs preliminary voltage transformation on the clock signal before it is used to drive subsequent stages. By pre-reducing the voltage amplitude of the clock signal through the transistor switching network, the circuit ensures that the signal has appropriate voltage levels for low power consumption while maintaining sufficient amplitude for effective signal transmission in downstream circuits.
Solution Approach 2:
The second transistor acts as an intermediary element that transforms the high-voltage clock signal from the first transistor into a low-voltage signal suitable for output. This intermediary transformation ensures that the voltage is reduced to appropriate levels for power efficiency while the signal integrity and amplitude are maintained for proper signal transmission.
Data Source
AI summary
The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.