Level Shifter Circuit for Low-Voltage Display Driver Signals
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the drive voltage of driver circuits to achieve low power consumption, particularly in large display devices like liquid crystal televisions, where the amplitude voltage of clock signals is high, leading to increased power consumption.
Innovation Solution
A semiconductor device is designed with a specific configuration of transistors and wiring connections that allow for the amplification of input signals, reducing the amplitude voltage of output signals and thereby lowering the drive voltage of the driver circuit, using a level shifter circuit to increase the amplitude voltage of digital signals while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amplitude voltage of clock signals is increased to ensure proper operation of the driver circuit, then the reliability of signal transmission is improved, but the power consumption of the driver circuit increases
Solution Approach 1:
The driver circuit is divided into multiple stages including a first inverter circuit and a second inverter circuit with different amplitude voltages. The first inverter circuit operates at a lower amplitude voltage for clock signals, while the second inverter circuit operates at a higher amplitude voltage for output signals. This segmentation allows the circuit to maintain reliability where needed while reducing power consumption in clock signal processing.
Solution Approach 2:
Different parts of the driver circuit are assigned different amplitude voltage characteristics. Specifically, the first inverter circuit uses a first amplitude voltage for clock signals, while the second inverter circuit uses a second amplitude voltage that is higher than the first. This local differentiation enables the circuit to optimize both power consumption and signal transmission reliability in different regions.
2Use of energy by moving object
If additional inverter circuits are added to reduce drive voltage, then the power consumption is reduced, but the device complexity increases
Solution Approach 1:
The first inverter circuit serves multiple functions: it inverts clock signals and simultaneously steps down their amplitude voltage from the second amplitude voltage to the first amplitude voltage. This multi-functionality reduces the need for separate voltage conversion circuits, thereby limiting the increase in device complexity while achieving power consumption reduction.
Solution Approach 2:
The invention changes the amplitude voltage parameter of clock signals as they pass through the first inverter circuit. The circuit is designed to accept clock signals at a second amplitude voltage and output them at a first amplitude voltage, effectively using parameter transformation to reduce power consumption without adding complex voltage conversion stages.
Data Source
AI summary
The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.