Clock Duty Cycle Calibration for Level Shifters Across Voltage Domains
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the decreasing operating voltages affect their performance, particularly in level shifter circuits that operate across different voltage domains, leading to challenges in maintaining accurate clock duty cycles and robustness against corrupted input waveforms.
Innovation Solution
A clock duty cycle adjustment and calibration circuit is introduced, comprising a ring oscillator, level shifters, a duty cycle adjustment circuit, and a duty cycle calibration circuit, which generates and adjusts phase clock signals across voltage domains without analog voltage measurement, ensuring robustness and independence from input duty cycles, using filters for higher frequencies to occupy less area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If level shifter circuits operate across different voltage domains with decreasing operating voltages, then IC miniaturization and complexity increase, but clock duty cycle accuracy deteriorates and performance is affected
Solution Approach 1:
The patent introduces a duty cycle calibration circuit as an intermediary component that measures and adjusts the duty cycle of clock signals after they pass through level shifters. This calibration circuit acts as a mediator between the voltage domain translation process and the final clock signal quality, compensating for duty cycle distortion without requiring changes to the core level shifter design or operating voltage constraints.
Solution Approach 2:
The patent implements a feedback mechanism where the duty cycle calibration circuit continuously monitors the duty cycle of output clock signals and generates correction signals to adjust the duty cycle back to the desired value. This closed-loop feedback system ensures that duty cycle accuracy is maintained despite variations in operating voltage and level shifter characteristics, directly addressing the precision deterioration problem.
2Manufacturing precision
If traditional duty cycle adjustment methods are used, then clock duty cycle can be adjusted, but the circuit complexity increases and area is consumed
Solution Approach 1:
The duty cycle calibration circuit is designed to be self-calibrating, automatically measuring its own output duty cycle and adjusting its internal parameters without external intervention. The circuit uses its own output clock signals to generate calibration data, eliminating the need for external test equipment or complex control systems, thereby reducing overall system complexity while maintaining high duty cycle accuracy.
Solution Approach 2:
The patent adjusts duty cycle by changing timing parameters of clock signal edges rather than using complex circuit topologies. The calibration circuit modifies the propagation delay or edge timing of clock signals through simple parameter adjustments in timing control circuits, achieving precise duty cycle control with minimal additional circuitry compared to structural modification approaches.
3Area of stationary object
If filters are used for higher frequencies, then area usage is reduced, but frequency consistency and robustness against corrupted input waveforms must be maintained
Solution Approach 1:
The patent replaces traditional analog voltage measurement and filtering mechanisms with digital signal processing techniques. Instead of using large analog filters to handle high-frequency clock signals, the system uses digital logic circuits that can operate at higher frequencies with smaller area while providing equivalent or superior noise rejection and waveform validation capabilities through logical comparison and error detection methods.
Data Source
AI summary
A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. Each level shifter is configured to output a corresponding phase clock signal of the first set of phase clock signals. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to at least one of a first or second phase clock signal of the first set of phase clock signals or a set of control signals. The first clock output signal has a second duty cycle. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.