Level Shifter Using Symmetric Reference Nodes for Duty Cycle Stability
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Solution Overview
Problem
Existing level shifters in semiconductor circuits suffer from substantial distortion and variation in duty cycle due to PVT (process voltage temperature) variations, often requiring more gates than necessary and using poorly aligned internal reference signals.
Innovation Solution
The implementation of a level shifter with cross-coupled/latch circuitry, symmetric reference nodes, and output circuitry that sets the output signal based on the rising edges of these nodes, reducing distortion and fluctuation by ensuring balanced rise and fall transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing level shifter circuits are used to convert voltage levels, then voltage level conversion is achieved, but duty cycle distortion and variation occur due to PVT variations
Solution Approach 1:
The patent employs asymmetric rise and fall path timing adjustment where the rise path includes a first delay element and the fall path includes a second delay element with different delay characteristics. This asymmetric design compensates for PVT variations by independently optimizing each transition path, thereby reducing duty cycle distortion while maintaining voltage level conversion functionality.
2Reliability
If more gates are used in existing level shifters to improve duty cycle, then duty cycle stability improves, but device complexity increases
Solution Approach 1:
The patent integrates multiple functions into unified circuit blocks: the cross-coupled latch circuitry simultaneously provides level conversion and duty cycle stabilization, while the delay elements serve both timing adjustment and PVT compensation functions. This multi-functionality achieves duty cycle stability without proportionally increasing gate count.
Solution Approach 2:
The level shifter is segmented into distinct functional modules: input circuitry, cross-coupled latch circuitry with first and second reference nodes, and output circuitry with independent delay elements for rise and fall paths. This segmentation allows targeted optimization of each module to collectively achieve duty cycle stability with minimal overall complexity.
3Speed
If internal reference signals are used in existing level shifters, then level conversion is achieved, but time domain misalignment occurs causing duty cycle variation
Solution Approach 1:
The patent introduces delay elements in advance of the output stage that pre-adjust the timing of reference node transitions. By preliminarily compensating for anticipated PVT-induced timing shifts, the circuit maintains accurate time domain alignment between rising and falling edges, ensuring consistent duty cycle under varying conditions.
Data Source
AI summary
Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, the first reference node and the second reference node are symmetric nodes having signals that are inverse to each other.