Voltage-Controlled Level Shifter for 50% Duty Ratio
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Solution Overview
Problem
Conventional level shifters in semiconductor devices face challenges in precisely controlling the duty ratio of output signals, especially in high-speed systems where slight signal distortions significantly impact performance, due to varying delay times and transistor size effects.
Innovation Solution
A level shifter with a voltage-controlled delay unit and a duty ratio detector that adjusts the delay time of input signals and outputs level-shifted signals with precise control over the duty ratio, using a capacitor and NMOS transistors to equalize rising and falling delay times, and a method that involves inverting input signals and using MRS or fuse options to control delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional level shifter is used to shift voltage levels, then voltage level conversion is achieved, but the duty ratio of the output signal cannot be precisely controlled
Solution Approach 1:
The patent implements a feedback mechanism where the duty ratio detector monitors the output signal's duty ratio and feeds this information back to the voltage-controlled delay unit. This closed-loop feedback system enables the delay unit to adjust the delay time dynamically, ensuring the duty ratio is precisely maintained at the desired level despite variations in circuit parameters or operating conditions.
Solution Approach 2:
The patent replaces traditional mechanical or fixed-delay timing mechanisms with a voltage-controlled delay unit that uses electrical signals to control delay time. By using voltage control instead of fixed mechanical delays, the system achieves precise and adjustable duty ratio control through electrical parameters, enabling dynamic adaptation to different operating conditions.
2Speed
If delay times are reduced for high-speed operation, then operating speed is improved, but duty ratio distortion increases
Solution Approach 1:
The patent makes the delay time dynamic by introducing a voltage-controlled delay unit whose delay characteristic can be adjusted in real-time. Instead of using fixed, static delay elements, the system dynamically adapts the delay time based on feedback from the duty ratio detector, allowing the circuit to maintain accurate duty ratio control while operating at high speeds by optimizing the delay time according to actual signal conditions.
Solution Approach 2:
The patent changes the delay time parameter dynamically through voltage control of the delay unit. By adjusting the control voltage applied to the delay unit, the system can modify the delay time parameter to compensate for speed-related distortions, ensuring that even at high operating speeds, the duty ratio remains accurately controlled through parameter adaptation.
3Reliability
If transistor sizes are optimized for performance, then operating characteristics are improved, but delay time variations between rising and falling edges increase
Solution Approach 1:
The patent introduces a voltage-controlled delay unit as an intermediary element between the input signal and the level shifting stage. This intermediary component acts as a buffer that can compensate for delay time differences by adding adjustable delay to the inverted signal, thereby equalizing the rising and falling edge delays despite transistor size optimizations in the level shifting circuit.
Solution Approach 2:
The patent applies preliminary anti-action by pre-compensating for the delay time difference through the voltage-controlled delay unit before the signal undergoes level shifting. By anticipating and counteracting the delay imbalance caused by transistor size optimizations, the system ensures that the inverted signal arrives at the appropriate timing to maintain equal rising and falling delays in the final output.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise control of the duty ratio of output signals, ensuring a 50% duty cycle, thereby improving the operating characteristics of high-speed semiconductor devices by equalizing delay times and maintaining consistent signal performance.
Implementation Method 1
a voltage-controlled delay unit configured to receive an input signal, invert a level of the input signal, and delay the inverted input signal to output a delayed inverted signal, a delay time of the delayed inverted signal being adjusted in a manner that performs a charging operation with the inverted signal
Data Source
AI summary
A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.