Voltage Level Shifter With Dynamic Pull-Up Paths for Faster Rising Edges
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional level shift circuits exhibit long output rising time delays, which constrain system clock speeds and increase power dissipation, while attempts to reduce delays often increase standby current.
Innovation Solution
A voltage level shifter design featuring a first pull-up transistor, a first pull-down transistor, and a bias transistor, with additional pull-up paths that are activated during transitions to assist in voltage shifting, allowing for faster voltage transitions while maintaining low standby current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shift circuit design is used, then circuit simplicity is maintained, but output rising time delay increases
Solution Approach 1:
The pull-up function is segmented into two separate paths: a main pull-up transistor and an additional pull-up path with its own transistor. This segmentation allows the additional path to provide extra current during transitions without requiring complete redesign of the original simple circuit structure.
Solution Approach 2:
The additional pull-up path provides excessive pull-up current during transitions, more than what the main pull-up transistor alone could provide. This excessive action reduces the rising time delay, and the path is designed to be deactivated when not needed to avoid continuous power consumption.
2Speed
If additional pull-up current is provided to reduce rising time delay, then output rising time improves, but standby current increases
Solution Approach 1:
The additional pull-up path is designed to be dynamically controllable, switching between active and inactive states based on circuit conditions. This dynamic behavior allows the path to provide current only when needed for transitions, reducing standby current while maintaining fast rising times.
Solution Approach 2:
The additional pull-up path is automatically activated and deactivated based on the state of the main pull-up transistor and circuit conditions, without requiring external control signals. The path self-regulates its current contribution to reduce standby power while providing assistance during transitions.
3Speed
If stronger pull-up transistor is used, then output rising time decreases, but power dissipation increases
Solution Approach 1:
The pull-up current provision is segmented between a main pull-up transistor and an additional pull-up path. This segmentation allows the additional path to contribute current only during transitions when needed, rather than continuously, thereby reducing overall power dissipation while achieving faster rising times.
Solution Approach 2:
The additional pull-up path operates periodically or transiently during voltage transitions rather than continuously. This periodic activation provides the necessary current bursts to reduce rising time delay while minimizing continuous power dissipation during steady states.
Data Source
AI summary
Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias transistor. A gate of the first bias transistor is coupled with a bias voltage signal. The voltage level shifter further includes a first additional pull up path coupled with the high voltage signal and a first node between the first pull up transistor and the first pull down transistor, and an output signal associated with the first node. The output signal is a level shifted voltage responsive to the input signal.