Level Shifter Pull-Up Circuit for Edge Skew Compensation
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Solution Overview
Problem
Modern integrated circuit devices face challenges in interfacing with previous technology generations due to differences in CMOS voltage levels, requiring robust level shifters that also address duty cycle and delay issues across different voltage domains.
Innovation Solution
A level shifter with additional pull-up circuitry and an edge rate compensation stage, featuring symmetrical construction and operation, is implemented to enhance rise time and reduce edge rate differences, thereby improving duty cycle and response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If differently sized pull-up and pull-down transistors are used to improve writeability, then the N-type pull-down transistor can be made larger than the P-type pull-up transistor, but this introduces skew between the OUT and OUTX outputs and creates rise time faster than fall time
Solution Approach 1:
The patent applies asymmetry by using differently sized transistors (larger N-type pull-down than P-type pull-up) to optimize writeability for specific operations. This deliberate asymmetry improves ease of manufacture for write operations but creates the technical contradiction by introducing output skew and unequal rise/fall times that must be compensated for in the circuit design.
Solution Approach 2:
The patent changes transistor size parameters to optimize writeability, making the N-type pull-down transistor larger than the P-type pull-up transistor. This parameter change improves write operations but directly causes the skew between OUT and OUTX outputs and the rise time faster than fall time issue, requiring additional compensation circuitry.
2Adaptability or versatility
If a level shifter is coupled to a power supply with a different voltage to enable voltage level shifting, then the level shifter can provide output voltages corresponding to the power supply voltage, but this creates complexity in interfacing between different CMOS voltage levels
Solution Approach 1:
The level shifter acts as an intermediary device between different CMOS voltage domains. It is coupled to a power supply with a different voltage than the input signals, enabling it to translate voltage levels between domains. This intermediary approach solves the voltage level mismatch problem but inherently adds device complexity to the interface design.
3Productivity
If the N-type pull-down transistor is made larger than the P-type pull-up transistor to improve writeability, then write operations are enhanced, but the rise time becomes faster than the fall time, introducing skew between outputs
Solution Approach 1:
The transistor size parameters are changed to optimize write operation productivity, with the N-type pull-down transistor made larger than the P-type pull-up transistor. This parameter optimization enhances write efficiency but directly causes the rise time to be faster than fall time, introducing output skew that represents a loss of time synchronization.
Data Source
AI summary
A level shifter includes first and second input terminals, first and second output terminals, first pull-down circuitry operable to pull down one of the first and second output terminals responsive to signals present on the first and second input terminals, first pull-up circuitry operable to pull up the first output terminal responsive to a signal present on the second output terminal or pull up the second output terminal responsive to a signal present on the first output terminal, and second pull-up circuitry operable to pull up one of the first and second output terminals responsive to the signals present on the first and second input terminals.