Level Shifter Layout for ESD-Robust Semiconductor I/O Cells

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Solution Overview

Problem

Existing semiconductor devices face issues where the level shifter circuit is destroyed prior to the ESD protection circuit during ESD surge tests, compromising the desired ESD resistance, especially in advanced CMOS technologies like the 7 nm generation.

Innovation Solution

The semiconductor device is designed with the core power supply cell arranged in a third region between the input/output cell and the core logic circuit, ensuring the core power supply cell is not in the same row as the input/output cell, with specific dimensions to minimize wiring resistance and protect the level shifter circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the core power supply cell is arranged in the same row as the input/output cell, then the wiring length is reduced and wiring resistance is minimized, but the level shifter circuit is destroyed prior to the ESD protection circuit during ESD surge

Engineering Contradiction:

ImproveESD resistanceVSAvoiddamage to level shifter circuit

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The semiconductor device is divided into distinct functional regions: an input/output cell region, a core logic circuit region, and a core power supply cell region positioned in between. This spatial segmentation isolates the ESD protection circuit in the core power supply cell from the vulnerable level shifter circuit in the input/output cell, preventing ESD surge from destroying the level shifter before the protection circuit activates.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The core power supply cell containing the ESD protection circuit acts as an intermediary barrier positioned between the input/output cell and the core logic circuit. This intermediary structure intercepts and protects against ESD surges before they can reach and destroy the level shifter circuit in the input/output cell.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the core power supply cell is arranged far from the input/output cell, then the level shifter circuit is protected from ESD surge, but the wiring resistance increases

Engineering Contradiction:

Improveprotection of level shifter circuitVSAvoidwiring resistance

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The core power supply cell is positioned in the intermediate region between the input/output cell and core logic circuit, creating a localized ESD protection zone. This local positioning provides sufficient protection distance to save the level shifter circuit while maintaining acceptable wiring resistance levels for power supply delivery.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12464826B2Semiconductor device

Publication Date: 2025.11.04 RENESAS ELECTRONICS CORP

AI summary

A semiconductor device includes an input/output cell, an IO power supply cell, a core power supply cell, and a core logic circuit arranged on a chip, and the core power supply cell includes an ESD protection circuit. The input/output cell includes a level shifter circuit and the level shifter circuit is arranged in the input/output cell. The core logic circuit is arranged outside the input/output cell. The core power supply cell is not arranged in the same row as the input/output cell, but is arranged in a third region provided between a first region in which the input/output cell and the IO power supply cell are arranged and a second region in which the core logic circuit is arranged.