Level Shifter Circuit With Charge-Discharge Balancing for Fast HV Switching
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Solution Overview
Problem
High-voltage components in electronic devices do not operate properly or operate with delays when driven by low operation voltages, leading to improper device operation.
Innovation Solution
A level shifter circuit comprising a bias-voltage generation circuit, charge-discharge balancer circuit, and high-voltage NMOS transistors, which generate stable control voltages and processed signals to quickly switch high-voltage components, using high-voltage and low-voltage processing circuits to synchronize signal phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If high-voltage components are driven by low operation voltages, then power consumption is reduced, but the high-voltage component may not operate or operates with delay
Solution Approach 1:
The patent introduces a level shifter circuit as an intermediary between low-voltage and high-voltage domains. This circuit includes voltage translation functionality that converts low-voltage control signals into appropriate high-voltage signals, enabling high-voltage components to be controlled by low-voltage logic while maintaining proper operation. The level shifter acts as a mediator that resolves the voltage level mismatch without requiring high-voltage operation throughout the entire system.
Solution Approach 2:
The patent employs dynamic voltage scaling and threshold voltage adjustment techniques. By changing the voltage parameters adaptively - using low voltage for normal operation and switching to appropriate high voltage levels only when needed - the system reduces overall power consumption while ensuring high-voltage components operate reliably when required. This parameter change approach allows the system to optimize between power savings and operational reliability.
2Use of energy by stationary object
If high-voltage components are driven by low operation voltages, then power consumption is reduced, but switching speed decreases causing delays
Solution Approach 1:
The patent implements preliminary charging of parasitic capacitances and pre-positioning of voltage levels before switching events. The level shifter circuit prepares the voltage transitions in advance, and clock signal timing is optimized to account for propagation delays. This preliminary action ensures that when switching is required, the high-voltage components can transition rapidly without being limited by slow voltage buildup from low-voltage operation.
Solution Approach 2:
The patent utilizes periodic clock signals with optimized duty cycles and frequencies to drive the high-voltage components. By using periodic action, the system can maintain components in a ready state during active periods while consuming minimal power during idle periods. The periodic switching allows high-voltage components to operate at full speed when needed while averaging out the power consumption over time.
Data Source
AI summary
A level shifter circuit including a bias-voltage generation circuit, a charge-discharge balancer circuit, a first high-voltage NMOS transistor, a second high-voltage NMOS transistor, a low-voltage processing circuit, and a high-voltage processing circuit is provided. The bias-voltage generation circuit generates a stable voltage. The charge-discharge balancer circuit generates a first control voltage and a second control voltage based on the stable voltage, a first processed signal, and a second processed signal. The first high-voltage NMOS transistor receives the first control voltage and a third processed signal. The second high-voltage NMOS transistor receives the second control voltage and a fourth processed signal. The low-voltage processing circuit processes an input signal to provide the first, second, third, and fourth processed signals. The high-voltage processing circuit generates an output signal based on the drain voltage of the first high-voltage NMOS transistor and the drain voltage of the second high-voltage NMOS transistor.