Level Shifter Circuit With Fast Transition and Low Current Hold
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Solution Overview
Problem
Existing digital electronic circuits face a trade-off between low current consumption and high transfer speed in voltage level shifters, with known designs compromising on these parameters, particularly in gate driver applications where fast switching is required.
Innovation Solution
The proposed level shifter incorporates parallel switch transistors and controller modules to manage transition periods and stabilization periods, reducing current consumption and transfer delay by controlling the activation and deactivation of switch transistors during signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shifter designs are used, then current consumption is reduced, but transfer delay increases
Solution Approach 1:
The level shifter circuit is segmented into multiple parallel paths with different functions: a first path for fast signal transition and a second path for maintaining low current consumption during stable states. This segmentation allows the circuit to optimize performance during transitions while minimizing power consumption during steady operation.
Solution Approach 2:
The circuit dynamically switches between different operational modes using control signals. During transition periods, the circuit activates fast switching paths; during stable periods, it switches to low-power paths. This dynamic adaptation resolves the contradiction between speed and power consumption.
2Loss of time
If fast switching is implemented, then transfer delay is reduced, but current consumption increases
Solution Approach 1:
The circuit employs periodic control signals to activate fast switching paths only during necessary transition periods. The control logic detects signal transitions and temporarily enables high-speed paths, then deactivates them during stable periods. This periodic activation reduces average current consumption while maintaining fast transfer delay when needed.
Solution Approach 2:
The circuit changes operational parameters dynamically based on signal state. During transitions, it switches to parameters optimized for speed (low resistance paths); during stable states, it switches to parameters optimized for low power (high resistance paths). This parameter switching resolves the trade-off between transfer delay and current consumption.
Data Source
AI summary
A level shifter includes a latch supplied at a first voltage, and first and second series connections of first and second switch elements and first and second biased elements in series with first and second branches of the latch respectively. Third and fourth switch elements are connected in parallel with the first and second series connections respectively. The input signal, at a voltage different from the first voltage, activates the third or fourth switch element during a transition period after a change of state of the input signal one way or the other to change the state of the latch, and deactivates the third or fourth switch element and activates the first or second switch element to maintain the state of the latch during a stabilization period following the transition period. The transition periods are shortened, reducing current consumption and transfer delay times.