Level Shifter Feedback Circuit for Structural Fault Testing
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Solution Overview
Problem
State-of-the-art system on chip devices (SOCs) lack structural testing of power domain crossings between digital synthesized logic and analog macros, leading to fault coverage holes in production test and functional safety.
Innovation Solution
A level shifter test circuit with feedback logic is introduced, incorporating XOR logic gates and end gates to protect output signals, allowing for structural testing of level shifters and detecting defects such as soft and latent defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If structural testing is not implemented at power domain crossings, then device complexity is reduced, but fault coverage is insufficient leading to reliability issues
Solution Approach 1:
The feedback logic is nested within the level shifter circuit by tapping the translated signal at the output of the level shifter and feeding it back through logic gates (XOR, AND, OR) to the input side. This nested structure enables structural testing without requiring external testing equipment, thereby improving fault coverage while minimizing additional circuit complexity.
Solution Approach 2:
A feedback path is introduced where the translated signal from the second power domain is fed back to the first power domain through logic gates. The feedback logic compares the original input signal with the translated and fed-back signal to detect faults, thereby improving reliability through continuous monitoring without significantly increasing device complexity.
2Difficulty of detecting and measuring
If feedback logic is added to enable structural testing, then fault detectability is improved, but device complexity increases
Solution Approach 1:
The feedback logic gates (XOR, AND, OR) are nested within the existing level shifter circuit structure, utilizing the translated signal path for testing purposes. This nesting approach enables defect detection while reusing existing circuit resources, thereby improving detectability without proportionally increasing overall circuit complexity.
Solution Approach 2:
The feedback logic serves multiple functions: it enables structural testing, detects faults in the level shifter, and validates signal translation accuracy. By making the feedback path multi-functional, the circuit achieves improved defect detectability while the same structure serves multiple purposes, reducing the need for additional dedicated testing components.
Data Source
AI summary
The present disclosure relates to a level shifter test circuit, a method of testing a level shifter test circuit, and a semiconductor chip. The circuit comprises a first level shifter for translating a signal from a first domain to a second domain. The first level shifter configured to receive the signal as an input from the first domain; and output a translated signal which has been translated by the first level shifter for the second domain, wherein the translated signal is split between a first output signal and a first level shifter feedback signal. The circuit further comprises test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.