Level Shifter Circuit With Floating PMOS Bulk to Prevent Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing level shifters experience unnecessary power consumption and reduced output voltage due to leakage currents and partial turn-on of PMOS transistors when junction breakdown voltages are exceeded, leading to inefficiencies in signal conversion between different power domains.
Innovation Solution
A level shifter design with NMOS and PMOS transistors where the bulk and source of PMOS transistors are disconnected, maintaining stable node voltages at 0V to prevent leakage currents and ensure full turn-on, using an RC circuit to adjust bulk voltages during mode changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage VPP10 is increased to 9V to achieve higher output voltage levels, then the output signal voltage level is improved, but leakage current flows through the NMOS transistor 10 causing unnecessary power consumption
Solution Approach 1:
The level shifter is divided into two separate stages: an input stage circuit that processes the input signal and generates an intermediate signal, and an output stage circuit that converts the intermediate signal to the final output signal. This segmentation allows each stage to operate within its optimal voltage range, preventing leakage current while maintaining high output voltage levels.
Solution Approach 2:
An intermediate signal is introduced as a mediator between the input signal and the output signal. The intermediate signal serves as a buffer that allows the input stage and output stage to operate independently at different voltage levels, eliminating the direct path for leakage current while enabling high voltage output.
2Reliability
If the voltage at node N10 is increased to greater than 0V to enable level conversion, then the output signal voltage level is improved, but the PMOS transistor 13 is partially turned on resulting in reduced supply current
Solution Approach 1:
The level shifter is divided into two separate stages: an input stage circuit that processes the input signal and generates an intermediate signal, and an output stage circuit that converts the intermediate signal to the final output signal. This segmentation allows each stage to operate within its optimal voltage range, preventing leakage current while maintaining high output voltage levels.
Solution Approach 2:
The patent changes the voltage parameter at the intermediate node (node N20) to remain at 0V even when the supply voltage VPP20 is increased to 9V. By maintaining this parameter at a fixed value, the PMOS transistor in the output stage remains fully turned on, ensuring maximum supply current flow while still achieving the desired high output voltage level.
Data Source
AI summary
A level shifter receives an input signal through an input terminal and converts the input signal to an output signal. The level shifter includes an input stage circuit and an output stage circuit. The input stage circuit receives the input signal. The input stage circuit includes an N-type transistor that has a gate coupled to the input terminal, a drain coupled to a first node, a source coupled to a ground, and a bulk connected to the source. The output stage circuit is coupled to an output terminal and the first node. The output stage circuit includes a P-type transistor that has a gate, a source coupled to the supply terminal, a drain coupled to the first node, and a bulk disconnected from the source. The output signal is generated at the output terminal. An inverted output signal is generated at the first node.