Level Shifter Circuit With Single-Step Gate Delay
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Solution Overview
Problem
Conventional level shifters for semiconductor devices face challenges in high-speed operations due to increased power consumption, leakage current, reduced operating speed, and deteriorated duty ratio, especially at frequencies above 500 MHz, primarily because they require two steps of gate delay and often malfunction at low supply voltages.
Innovation Solution
A level shifter design incorporating a pull-up signal generation unit, a pull-up unit, and a pull-down unit, utilizing a single PMOS transistor and a single NMOS transistor, with a capacitor and maintenance unit to synchronize phases and maintain a reference level, preventing simultaneous transistor activation and reducing gate delay to one step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shifter design with two steps of gate delay is used, then voltage level shifting from low to high is achieved, but operating speed is reduced and power consumption increases
Solution Approach 1:
The level shifter is divided into three functional units: pull-up signal generation unit, pull-up unit, and pull-down unit. Each unit performs a specific function with a single transistor, eliminating the need for two-step gate delay while maintaining voltage level shifting capability from low to high.
Solution Approach 2:
A pull-up signal is introduced as an intermediary element between the input signal and the output signal. This pull-up signal, generated at a voltage level higher than the input signal by the pull-up signal generation unit, enables direct single-step voltage level shifting without requiring sequential gate operations.
2Loss of energy
If conventional level shifter design is used, then voltage level shifting is achieved, but leakage current increases and power consumption increases
Solution Approach 1:
The invention extracts and eliminates the source of leakage current by using only one PMOS transistor and one NMOS transistor in separate pull-up and pull-down units, rather than having overlapping transistor operations in conventional designs. This configuration prevents simultaneous transistor activation that causes leakage current.
Solution Approach 2:
The pull-up signal generation unit automatically generates the necessary pull-up signal at the appropriate voltage level, and the maintenance unit keeps the pull-up signal at a reference level, enabling the system to self-regulate and prevent leakage current without additional control circuits.
3Productivity
If conventional level shifter design is used, then voltage level shifting is achieved, but duty ratio deteriorates at high frequencies
Solution Approach 1:
The pull-up signal is generated in advance at a voltage level higher than the input signal before the actual level shifting operation. The maintenance unit prepares to keep the pull-up signal at a reference level, ensuring that the pull-up unit can immediately respond to input signal changes without delay, thereby maintaining stable duty ratio at high frequencies above 500 MHz.
4Adaptability or versatility
If conventional level shifter design is used, then voltage level shifting from low to high is achieved, but the design becomes difficult to implement at high speeds
Solution Approach 1:
Each functional unit (pull-up signal generation unit, pull-up unit, pull-down unit) is designed with specific local characteristics optimized for its function. The pull-up signal generation unit specifically generates signals at voltage levels suitable for high-speed operation, while the maintenance unit specifically maintains the reference level, enabling the overall system to operate adaptably at frequencies above 1 GHz with simplified transistor configuration.
Data Source
AI summary
A level shifter and method of level shifting between an input signal and an output signal which may realize improvement s in operating speed and reductions in power consumption. An example level shifter may include a pull-up signal generation unit outputting a pull-up signal at a voltage level that is a given voltage level higher than a voltage level of an input signal, a pull-up unit pulling-up an output signal in response to the pull-up signal to generate the output signal with a shifted level, and a pull-down unit pulling-down the output signal in response to the input signal.