Current-Steering Level Shifter for Fast High-Voltage Gate Drive

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Solution Overview

Problem

In portable electronics, integrating power management and digital circuitry on a single chip faces challenges due to the mismatch between the voltage tolerance of CMOS transistors and battery voltages, requiring effective level-shifting circuitry to control high and low-side power transistors in half-bridge or full-bridge circuits without damaging the transistors.

Innovation Solution

A level-shifter circuit that includes a control stage and a logic driver, capable of steering current from one control node to another based on an input signal to set initial voltages in both control nodes, allowing the generation of an output signal in a high voltage domain from a low voltage input signal, and a high-side gate driver circuit that generates a voltage corresponding to a logic-low signal in the high voltage domain, enabling level-shifting of input signals from a low voltage domain to a high voltage domain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If battery voltage is increased to deliver more power, then power delivery capability is improved, but transistor breakdown risk increases

Engineering Contradiction:
Improvepower delivery capabilityVSAvoidtransistor breakdown risk
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

A level-shifter circuit is introduced as an intermediary between the low-voltage digital control logic and the high-voltage power transistors. The level-shifter translates control signals from the low-voltage domain (e.g., 1.8V) to the high-voltage domain (e.g., 5.5V), enabling the power transistors to be controlled safely without exposing the digital logic to damaging voltages while maintaining high power delivery capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system is segmented into distinct voltage domains: a low-voltage domain for digital control logic and a high-voltage domain for power delivery. This segmentation allows each domain to operate at its optimal voltage level, with the low-voltage logic protected from high-voltage stress while the high-voltage power stage delivers maximum power.

Inventive Principle:
Principle #1Segmentation

2Speed

If digital CMOS process is optimized for switching speed, then logic gate count and switching speed are improved, but voltage tolerance decreases

Engineering Contradiction:
Improveswitching speedVSAvoidvoltage tolerance
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The level-shifter circuit acts as a mediator that interfaces between the fast-switching low-voltage digital CMOS logic and the high-voltage power transistors. It preserves the high switching speed of the digital logic while translating signals to the high-voltage domain, preventing voltage tolerance issues without compromising speed performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If level-shifting circuitry is added to protect transistors, then transistor safety is improved, but circuit complexity increases

Engineering Contradiction:
Improvetransistor safetyVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A dedicated level-shifter circuit is added as an intermediary component between the digital control logic and power transistors. While this increases component count, it provides essential voltage translation functionality that simplifies the overall system design by clearly separating voltage domains and protecting sensitive digital logic from high-voltage stress.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7994819B2Level-shifter circuit
Publication Date: 2011.08.09 TEXAS INSTRUMENTS INC
  • US7994819B2 patent drawing
  • US7994819B2 patent drawing
  • US7994819B2 patent drawing

AI summary

One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an input signal to set a first initial voltage at the first control node and a second initial voltage at the second control node, the input signal having logic-high and logic-low voltage magnitudes that occupy a low voltage domain. The circuit also includes a logic driver that is coupled to the second control node and is referenced in a high voltage domain. The logic driver can be configured to provide an output signal having logic-high and logic-low voltage magnitudes that occupy the high voltage domain based on the second initial voltage.