Level Shifter Gate Driving Circuit Asymmetric Clock Waveform
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Solution Overview
Problem
Typical display devices face issues with insufficient charging of sub-pixels, leading to poor image quality due to inadequate charging time and differences in gate signal characteristics, which can cause gate driving malfunctions.
Innovation Solution
A level shifter and gate driving circuit are designed to reduce differences in gate signal characteristics by controlling the rising and falling characteristics of clock signals, using output buffer circuits with pull-up and pull-down transistors connected to gate lines, and a control circuit to manage these transistors, allowing for efficient charging and reduced area occupancy on the display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the non-display area of the display panel is reduced, then design freedom and design quality are improved, but it becomes difficult to arrange various lines and circuit elements
Solution Approach 1:
The gate driving circuit is moved from a planar arrangement in the non-display area to a three-dimensional stacked configuration within the display area. Multiple circuit layers are vertically stacked above the substrate, allowing circuit elements to be arranged in the vertical dimension rather than competing for horizontal space, thus reducing the non-display area while maintaining circuit functionality
Solution Approach 2:
The circuit elements are nested in a hierarchical stack structure where different circuit components are placed in successive layers above the substrate. The level shifter, output buffer circuits, and other components are vertically stacked and interconnected through vias, creating a nested configuration that maximizes space utilization within the display area
2Productivity
If charging time is insufficient, then productivity is improved, but image quality deteriorates due to insufficient capacitor charging
Solution Approach 1:
The gate signal waveform is dynamically adjusted with asymmetric rising and falling durations. The rising duration is extended to ensure adequate charging time for the capacitor, while the falling duration is shortened to maintain overall signal efficiency. This dynamic waveform shaping allows the capacitor to charge fully during the extended rising phase while keeping the total period short for high productivity
Solution Approach 2:
The clock signal parameters are modified by introducing different rising and falling durations, creating an asymmetric waveform. This parameter change allows the charging phase (rising duration) to be sufficiently long for complete capacitor charging, while the discharging phase (falling duration) is optimized to maintain high switching frequency and productivity
3Device complexity
If gate signal characteristics differ, then device complexity is reduced, but gate driving malfunctions occur leading to poor image quality
Solution Approach 1:
The level shifter circuit incorporates feedback mechanisms that monitor the output gate signal characteristics and adjust the clock signal parameters accordingly. This feedback ensures that all gate signals maintain consistent rising and falling durations despite variations in loading conditions, preventing gate driving malfunctions while keeping the circuit design relatively simple
Solution Approach 2:
The level shifter circuit equalizes the waveform characteristics of multiple clock signals by adjusting their rising and falling durations to be substantially identical. This equipotential approach ensures that all gate signals operate under uniform conditions, improving reliability without requiring complex individual signal conditioning circuits for each gate line
Data Source
AI summary
A display device includes a level shifter and a gate driving circuit that can reduce differences in characteristics among gate signals to improve image quality by controlling a signal waveform of a first clock signal of the m number of clock signals different from a signal waveform of an m-th clock signal when m number of gate signals is output by using m number of clock signals.