Level Shifter Circuit for GHz Signal Voltage Conversion
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Solution Overview
Problem
Existing level shifter circuits are inadequate for high-frequency signals, such as those used in Bluetooth and 5G applications, due to nonlinear increases in resistance and decreased charging speeds of parasitic capacitance, which hinder efficient voltage changes.
Innovation Solution
A level shifter circuit design incorporating a first and second impedance element, each with at least three terminals, and transistors of different conductivity types, where the impedance elements include resistance and capacitance elements connected between specific terminals to accelerate charge and discharge operations, enabling efficient voltage transformation for high-frequency signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional level shifter circuit is used, then it can handle low-frequency signals (several tens of MHz), but it cannot handle high-frequency signals (several GHz) due to nonlinear resistance increase and decreased charging speed
Solution Approach 1:
The circuit is divided into multiple parallel paths: a first path with a first transistor for charging the drain parasitic capacitance, and a second path with a second transistor for discharging it. This segmentation allows independent optimization of charging and discharging operations, enabling the circuit to handle high-frequency signals effectively.
Solution Approach 2:
The circuit dynamically switches between charging and discharging modes based on the input signal phase. During the first phase, the first transistor charges the parasitic capacitance while the second transistor is off. During the second phase, the second transistor discharges the capacitance while the first transistor is off. This dynamic operation maintains linear resistance characteristics even at high frequencies.
2Productivity
If the fourth NMOS transistor charges the drain parasitic capacitance, then the charging action occurs, but the third NMOS transistor turns off and cannot contribute to discharge
Solution Approach 1:
The circuit separates the charging and discharging functions into distinct parallel paths with dedicated transistors. The first transistor handles charging while the second transistor handles discharging, allowing both operations to be performed independently and simultaneously without interference, thus maintaining simplicity despite enhanced functionality.
3Device complexity
If the resistance value of the fourth NMOS transistor nonlinearly increases, then the charging speed of drain parasitic capacitance sharply decreases, but the circuit structure remains simple
Solution Approach 1:
By segmenting the charging and discharging paths, the circuit avoids the nonlinear resistance increase problem that occurs in conventional single-path designs. Each transistor operates in its optimal region, maintaining linear resistance characteristics and ensuring fast charging and discharging speeds.
Solution Approach 2:
The circuit changes the operational parameters by using different transistors for charging and discharging, allowing each transistor to be optimized for its specific function. This parameter optimization maintains linear resistance characteristics and ensures high-speed operation at frequencies up to several GHz.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed level shifter circuit effectively accelerates charge and discharge operations, allowing it to handle high-frequency signals of several GHz, reducing power consumption and improving performance for both high-frequency and low-frequency inputs.
Implementation Method 1
as drain parasitic capacitance of the first NMOS transistor is charged, a resistance value of the fourth NMOS transistor nonlinearly increases
Implementation Method 2
a resistance value of the fourth NMOS transistor nonlinearly increases
Data Source
AI summary
Provided is a level shifter circuit that changes a voltage of a high-frequency input signal to output. Provided is a level shifter circuit provided with a first input terminal and a second input terminal to each of which an input signal having a level between a first potential level and a first reference potential level is input, a first output terminal and a second output terminal from each of which an output signal having a level between a second potential level higher than the first potential level and a second reference potential level is output, a second potential supply node that supplies a voltage at the second potential level, a reference potential supply node that supplies a voltage at the second reference potential level, first and second impedance elements, first to fourth transistors, and first and second nodes, in which each of the first impedance element and the second impedance element includes at least three terminals.