Intermediate-Voltage Level Shifter for Low-Resistance High-Voltage Drive
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Solution Overview
Problem
Conventional level shifters face challenges in maintaining current drive capability and breakdown voltage across a wide voltage range, leading to increased circuit size and output resistance, which affects the reliability and endurance of non-volatile memory cells during programming and erasing operations.
Innovation Solution
A level shifter design incorporating a first latch between a power supply voltage and an intermediate voltage and a second latch between ground and another intermediate voltage, ensuring these voltages do not exceed transistor breakdown voltages, thereby maintaining low output resistance without increasing the number of transistors in the output path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of transistors is increased to increase current drive capability, then current drive capability is improved, but circuit size increases
Solution Approach 1:
The patent changes the voltage parameter from a single voltage level to multiple intermediate voltage levels (first intermediate voltage and second intermediate voltage). This allows the use of smaller transistors operating at lower voltage differences, thereby maintaining current drive capability while reducing transistor size and overall circuit area.
2Reliability
If transistors are added to address breakdown voltage, then breakdown voltage protection is improved, but circuit size increases and output resistance increases
Solution Approach 1:
The patent introduces intermediate voltage levels as mediators between the high voltage (VHI) and ground. These intermediate voltages act as buffer zones that protect transistors from direct exposure to full voltage differences, preventing breakdown without requiring additional protective transistors that would increase circuit size and output resistance.
Solution Approach 2:
The voltage range is segmented into multiple levels (VHI, first intermediate voltage, second intermediate voltage, ground). This segmentation breaks down the single large voltage difference into smaller steps, allowing transistors to operate within safe voltage differences while maintaining a compact circuit design.
3Reliability
If transistors are stacked to address breakdown voltage, then breakdown voltage protection is improved, but minimum operating voltage increases
Solution Approach 1:
The patent implements dynamic voltage level selection where the circuit can operate with different voltage differences depending on the operating conditions. By using intermediate voltages that can be dynamically adjusted or selected, the circuit maintains breakdown protection while allowing operation at lower minimum voltages compared to fixed stacked transistor configurations.
4Reliability
If the number of transistors in output path is increased, then breakdown voltage protection is improved, but output resistance increases and speed of operation decreases
Solution Approach 1:
The intermediate voltages serve as mediators that eliminate the need for additional transistors in the output path. By providing buffered voltage levels, the circuit achieves breakdown protection while maintaining a direct output path with minimal transistors, thereby preserving low output resistance and high speed of operation.
Data Source
AI summary
A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.