Level Shifter Heat and Delay Trade-off in HVICs
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Solution Overview
Problem
High-voltage integrated circuits (HVICs) face a trade-off between heat generation and propagation delay time in level shifters, as increasing driving frequencies leads to higher heat generation and reduced current-carrying capability, which in turn increases propagation delay time.
Innovation Solution
A semiconductor integrated circuit design featuring a high-voltage junction termination structure in a ring shape surrounding the high-side circuit region, with a level shifter and isolation region that includes a base region of higher impurity concentration, main electrode contact regions, and a control electrode to control surface potential, optimizing the effective channel width and parasitic capacitance to improve the trade-off between heat generation and delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the current-carrying capability of the level shifter is reduced to decrease heat generation, then heat generation is reduced, but the propagation delay time increases
Solution Approach 1:
The level shifter is divided into multiple smaller units arranged in parallel. Each unit handles a portion of the total current, distributing the heat generation across multiple elements while maintaining the overall current-carrying capability. This segmentation allows better thermal management without sacrificing signal transmission speed.
Solution Approach 2:
Different regions of the level shifter are designed with different impurity concentrations to optimize local performance. The base region has a higher impurity concentration than the substrate to reduce parasitic capacitance and improve switching speed, while the drift region maintains appropriate doping for breakdown voltage. This local optimization enables simultaneous improvement of speed and heat characteristics.
2Loss of time
If the effective channel width is increased to reduce propagation delay time, then propagation delay time is reduced, but parasitic capacitance increases
Solution Approach 1:
The impurity concentration of the base region is increased relative to the substrate. This parameter change reduces the depletion layer width and parasitic capacitance associated with the base-substrate junction.同时，the effective channel width is optimized to balance the trade-off between transmission speed and capacitance, achieving faster switching without excessive capacitance penalty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces heat generation while minimizing propagation delay time by optimizing the impurity concentrations and channel structure of the level shifter, thereby enhancing the overall performance of HVICs.
Implementation Method 1
a control electrode arranged over the base region at a position between the first and second main electrode contact regions in the plan view, so as to control a surface potential of the base region underneath
Implementation Method 2
a base region of a first conductivity type formed in an upper portion of a semiconductor substrate of the first conductivity type, an impurity concentration of the base region being higher than that of the substrate
Implementation Method 3
driving at higher frequencies results in an increase in heat generation, and therefore there is demand for reduced current-carrying capability in level shifters
Data Source
AI summary
A semiconductor integrated circuit includes a level shifter formed in a portion of a high-voltage junction termination structure and an isolation region formed surrounding the periphery of the level shifter. The level shifter includes a p-type base region formed in an upper portion of a p− substrate, an n− source region formed contacting the base region, an n+ drift region formed contacting the base region, a drain region formed in an upper portion of the drift region, and a control electrode that controls the voltage of the base region. In a planar pattern, an effective channel width defined by the width of the base region in a portion that overlaps with the control electrode is greater than the width of the drain region as measured along the same direction as the effective channel width.