Transient-Insensitive Level Shifter With Isolation Circuit
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Solution Overview
Problem
Existing level shifters face challenges in efficiently translating signals between independent voltage domains due to high power consumption, slow switching speeds, and asymmetric signal translation, particularly when using DEMOS transistors, which result in increased parasitic capacitance and bandwidth limitations.
Innovation Solution
A level shifter design that incorporates a latch with back-to-back inverters and an isolation circuit using less than two pairs of DEMOS transistors, along with asymmetric inverter supply voltages, to achieve zero quiescent power consumption and faster transition times by limiting DEMOS transistor usage and optimizing signal translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DEMOS transistors are used in level shifters, then voltage breakdown resistance is improved, but parasitic capacitance increases and bandwidth is limited
Solution Approach 1:
The level shifter is divided into multiple independent voltage domains (first voltage domain and second voltage domain) separated by isolation circuitry. This segmentation allows each domain to operate independently with its own voltage level, enabling the use of DEMOS transistors for high voltage protection while maintaining high bandwidth in low voltage domains through standard transistors.
Solution Approach 2:
Isolation circuitry acts as an intermediary between high voltage and low voltage domains. This intermediary contains the DEMOS transistors that provide voltage breakdown protection, while allowing high-frequency signals to pass through from low voltage to high voltage domains without being degraded by the parasitic capacitance of multiple DEMOS transistor pairs.
2Reliability
If multiple pairs of DEMOS transistors are used, then voltage protection is improved, but silicon area increases
Solution Approach 1:
The voltage protection function is extracted and concentrated into a single pair of DEMOS transistors within the isolation circuitry, rather than distributing multiple pairs throughout the level shifter. This extraction maintains comprehensive voltage protection while minimizing silicon area consumption by eliminating redundant DEMOS transistor pairs.
3Ease of operation
If conventional level shifters are used, then signal translation is achieved, but power consumption is high
Solution Approach 1:
The level shifter uses periodic switching action through isolated set and reset signals to translate voltage levels. The isolation circuitry enables controlled periodic transitions between voltage domains without requiring continuous power dissipation, achieving signal translation with minimal quiescent power consumption.
4Speed
If fast switching is achieved, then operating frequency is improved, but duty cycle is restricted
Solution Approach 1:
The switching function is segmented into independent set and reset operations that can be controlled separately. This segmentation allows the level shifter to achieve fast switching speeds for each transition while maintaining flexible duty cycles, as each voltage transition can be independently timed and controlled without being constrained by a minimum duty cycle requirement.
Data Source
AI summary
In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal. The second positive supply voltage is independent of the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.