Level Shifter Latch Pre-Charge for Small-Area Input Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing level shifter circuits face challenges in efficiently shifting data between voltage domains due to the need for sufficient drive strength, which often requires large input circuit devices to change the state of the keeper circuit, leading to area inefficiencies.
Innovation Solution
The proposed level shifter circuit employs a keeper circuit with cross-coupled inverter configurations and utilizes a clock signal to pre-charge or pre-discharge output nodes, allowing the input circuit to be smaller by reducing the need for high drive strength, as the clock signal manages the state changes of the keeper circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the input circuit uses large devices to provide sufficient drive strength, then the keeper circuit state can be changed reliably, but the circuit area increases
Solution Approach 1:
The patent applies pre-charge and pre-discharge mechanisms to the output nodes before data transition. During the pre-charge phase (when clock is low), both output nodes are charged to VDD. During the pre-discharge phase (when clock is high), both output nodes are discharged to ground. This preliminary action prepares the keeper circuit for state changes, allowing smaller input devices to reliably switch the keeper state without requiring large drive strength, thus resolving the contradiction between reliability and area.
Solution Approach 2:
The patent uses periodic clock signals to control the pre-charge and pre-discharge operations. The clock signal alternates between low and high states, periodically enabling the pre-charge transistor (when clock is low) and pre-discharge transistor (when clock is high). This periodic action ensures that the output nodes are properly prepared before each data transition, allowing reliable keeper state changes with smaller input devices, thereby resolving the area-reliability contradiction.
2Area of stationary object
If the input circuit devices are made smaller to reduce area, then area efficiency improves, but drive strength becomes insufficient to change keeper circuit state
Solution Approach 1:
By pre-charging and pre-discharging the output nodes before data transitions, the patent eliminates the need for large input devices. The pre-charge phase charges both output nodes to VDD, and the pre-discharge phase discharges them to ground, preparing the keeper circuit for reliable state changes even with small input devices. This preliminary action resolves the contradiction by enabling reliable operation with reduced area.
Solution Approach 2:
The patent introduces clock-controlled pre-charge and pre-discharge transistors as intermediary elements. These intermediaries prepare the output nodes by charging or discharging them to appropriate voltage levels before data transitions occur. This intermediary action allows small input devices to reliably switch the keeper state, resolving the contradiction between area efficiency and state change reliability.
3Area of stationary object
If pre-charge and pre-discharge operations are implemented, then input circuit area is reduced, but clock signal control complexity increases
Solution Approach 1:
The clock signal serves multiple functions: it controls the pre-charge operation (when low), controls the pre-discharge operation (when high), and coordinates the overall level shifter operation. By making the clock signal multi-functional, the patent avoids adding separate control signals for each operation, thereby reducing control complexity while still achieving area reduction through pre-charge and pre-discharge mechanisms.
Solution Approach 2:
The patent merges the control of pre-charge, pre-discharge, and level shifting operations into a single clock signal. The clock's low state enables pre-charge, the high state enables pre-discharge, and the transitions coordinate data latching. This consolidation of control functions into one signal reduces the overall control complexity despite adding pre-charge and pre-discharge functionality, resolving the contradiction between area reduction and control complexity.
Data Source
AI summary
A level shifter circuit and method of operating therefor. The level shifter circuit is coupled to receive a data signal via an input circuit, wherein the input circuit is in a first voltage domain. The level shifter circuit is also coupled to receive a clock signal from a second voltage domain. On a first portion of the clock cycle, true and complementary output nodes of the level shifter circuit (which are in the second voltage domain) are pulled to a first voltage by activation of respective pull transistors. On a second portion of the clock cycle, one of the true or complementary output nodes is pulled to a second voltage on a second voltage node by enabling the supply to the latch. Data is captured by the keeper, outputting true and complementary versions of the data signal in the second phase of the clock.