Edge-Triggered Level Shifter With LDMOS for Fast High-Voltage Switching
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Solution Overview
Problem
Existing level shifter circuits face challenges with large propagation delays, high fabrication costs, and power inefficiency due to the need for specialized high-voltage transistors, which increases complexity and reduces speed and efficiency.
Innovation Solution
The design employs an edge-triggered level shifter using standard low-voltage transistors and n-channel LDMOS transistors with lateral diffusion for high breakdown voltage, eliminating the need for multiple high-voltage transistor types, and incorporates current limiting and biasing mechanisms to manage voltage and current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If specialized high-voltage transistors are used to tolerate higher voltages, then voltage tolerance is improved, but fabrication cost and device complexity increase
Solution Approach 1:
The circuit is divided into low-voltage domain components (standard transistors, logic circuits) and high-voltage domain components (LDMOS transistors for current mirrors and output drivers). This segmentation allows each part to be optimized for its voltage domain, using standard fabrication processes for most components and only specialized LDMOS transistors where high voltage is required, thereby reducing overall fabrication complexity while maintaining voltage tolerance.
Solution Approach 2:
LDMOS transistors are designed to serve multiple functions: they act as current mirrors, output drivers, and voltage toleration elements in the high-voltage domain. This multi-functionality reduces the total number of different transistor types needed, simplifying the fabrication process while maintaining the ability to tolerate high voltages across different circuit functions.
2Reliability
If longer channel lengths and specialized layouts are used to improve voltage tolerance, then voltage tolerance is improved, but propagation delay increases
Solution Approach 1:
Different transistor types are used in different locations based on voltage requirements: standard transistors with shorter channels are used in the low-voltage domain where speed is critical, while LDMOS transistors with longer channels and specialized layouts are used only in the high-voltage domain where voltage tolerance is critical. This local differentiation optimizes both speed and voltage tolerance without compromising either.
Solution Approach 2:
The circuit uses dynamic voltage domain separation where signals are level-shifted between low-voltage and high-voltage domains. This allows the circuit to dynamically operate standard transistors at high speed in the low-voltage domain and only engage LDMOS transistors when high-voltage operation is required, minimizing the impact of longer channel lengths on overall propagation delay.
3Reliability
If additional fabrication steps (masks, etching, thick oxide growth) are added to create high-voltage transistors, then voltage tolerance is improved, but manufacturing cost increases
Solution Approach 1:
The fabrication process is segmented into standard CMOS steps (used for most low-voltage transistors) and specialized LDMOS steps (used only for high-voltage transistors). By segmenting the process, the expensive specialized steps are applied only where necessary rather than to all transistors, significantly reducing overall manufacturing cost while maintaining voltage tolerance in critical high-voltage components.
Solution Approach 2:
The design uses standard transistor geometries and layouts that can be copied from low-voltage designs, adapting them for LDMOS implementation where needed. This allows reuse of proven design patterns and reduces the need for completely new fabrication processes, lowering manufacturing costs while maintaining reliability.
4Device complexity
If standard low-voltage transistors are used throughout, then fabrication cost and complexity are reduced, but voltage tolerance decreases
Solution Approach 1:
The circuit implements local quality by using standard low-voltage transistors in the low-voltage domain where they provide sufficient performance and simplicity, while introducing LDMOS transistors only in the high-voltage domain where enhanced voltage tolerance is required. This localized approach maintains fabrication simplicity for the majority of the circuit while providing necessary voltage tolerance where needed.
Solution Approach 2:
Level shifters are used as intermediary components to translate signals between low-voltage and high-voltage domains. This allows standard low-voltage transistors to operate in their comfortable voltage range while still enabling the circuit to interface with and control high-voltage loads, effectively mediating between the simplicity of standard transistors and the voltage tolerance requirements of high-voltage applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces propagation delay, lowers power consumption, and simplifies fabrication while maintaining high-frequency operation and voltage tolerance, thereby improving circuit speed and reducing costs.
Implementation Method 1
n-channel LDMOS transistors with lateral diffusion for high breakdown voltage
Data Source
AI summary
A level shifter circuit uses standard n-channel and p-channel transistors except for a pair of Lateral-Diffusion Metal-Oxide-Semiconductor (LDMOS) transistors that have an added lateral diffusion under the gate between the source and the conduction channel, increasing the breakdown voltage. The source of each LDMOS transistor connects to a drain of a transient differential transistor that has its gate driven by a oneshot that generates a pulse after an input transition. After the pulse ends a holding differential transistor draws a smaller bias current from the LDMOS transistors. The source of each LDMOS transistor connects to the drain and gate of a p-channel sensing transistor that drives gates of mirror transistors generating mirrored currents to cross-coupled n-channel mirror transistors that drive both terminals of a bistable latch that holds the output using a floating ground between driver transistors of a Buck converter switched by the bistable latch.