Dual-Input Voltage Level Shifter for Core Power-Off Leakage Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional voltage level shifters exhibit poor leakage current characteristics, particularly during power saving modes when the core supply voltage is turned off, leading to degraded power consumption performance in integrated circuits.
Innovation Solution
The proposed voltage level shifter design includes multiple switch modules with specific transistor configurations and signal control mechanisms to prevent leakage currents by ensuring the output signal is determined by IO_INPUT signals when the core supply voltage is off, thereby isolating the core supply voltage from influencing the circuit operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional voltage level shifter circuit is used, then voltage level shifting function is achieved, but leakage current increases during power saving mode
Solution Approach 1:
The patent applies dynamics by making the circuit configuration changeable based on operating conditions. The switch controller dynamically adjusts the state of switches (first and second switches) depending on whether the core voltage is powered on or off, transitioning between different circuit configurations to optimize performance for each mode.
Solution Approach 2:
The patent introduces a switch controller as an intermediary component that mediates between the core voltage signal and the input/output voltage signals. This intermediary controls the switches to isolate or connect different circuit paths, preventing direct leakage paths while maintaining proper signal transmission.
2Use of energy by moving object
If core supply voltage is turned off for power saving, then power consumption is reduced, but leakage current paths are created
Solution Approach 1:
The patent applies preliminary action by proactively controlling the switches to open isolation paths before leakage currents can develop when the core voltage transitions to off state. The switch controller detects the core voltage state and preemptively configures the circuit to prevent leakage path formation.
Solution Approach 2:
The switch controller serves as an intermediary that decouples the core voltage domain from the input/output voltage domain when needed. By controlling the switches, it prevents the core voltage off state from directly causing leakage in the I/O section, allowing independent power management.
3Use of energy by moving object
If transistors are left in floating state when core voltage is off, then power saving is achieved, but circuit becomes unstable and triggers leakage
Solution Approach 1:
The patent makes the transistor states dynamic rather than static, adjusting them based on the core voltage operational state. When core voltage is off, the switches actively drive transistors to stable defined states rather than leaving them floating, preventing instability while maintaining power savings.
Solution Approach 2:
The circuit performs self-service by automatically adjusting its own configuration based on the core voltage state. The switch controller monitors and responds to core voltage conditions, self-regulating the switch states to prevent leakage without requiring external intervention.
Data Source
AI summary
A voltage level shifter includes a first switch module having a first transistor and a second transistor, each transistor having a drain, a gate, and a source, wherein the drains of the first and the second transistors are coupled to a first voltage terminal. The voltage level shifter further includes a second switch module coupled between the first switch module and a second voltage terminal, the second switch module including at least six transistors coupled each other, wherein each transistor of the second switch module having a gate for receiving a GATE signal, a GATEb signal, a CORE_INPUT signal, a CORE_INPUTb signal, an IO_INPUT signal, or an IO_INPUTb signal, respectively, wherein the second switch module is designed to produce an output signal at an output node in response to the IO_INPUTb signal and the IO_INPUT signal respectively, irrespective of the CORE_INPUTb signal and the CORE_INPUT signal when the GATE signal is logic low, thereby reducing a leakage current flowing from the first voltage terminal to the second voltage terminal.